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GPU: Corrected the size of the MUFU subop field, and removed incorrect "min" operation.
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parent
50ef2beb58
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@ -165,7 +165,6 @@ enum class SubOp : u64 {
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Lg2 = 0x3,
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Lg2 = 0x3,
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Rcp = 0x4,
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Rcp = 0x4,
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Rsq = 0x5,
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Rsq = 0x5,
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Min = 0x8,
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};
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};
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enum class F2iRoundingOp : u64 {
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enum class F2iRoundingOp : u64 {
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@ -209,7 +208,7 @@ union Instruction {
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} pred;
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} pred;
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BitField<19, 1, u64> negate_pred;
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BitField<19, 1, u64> negate_pred;
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BitField<20, 8, Register> gpr20;
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BitField<20, 8, Register> gpr20;
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BitField<20, 7, SubOp> sub_op;
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BitField<20, 4, SubOp> sub_op;
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BitField<28, 8, Register> gpr28;
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BitField<28, 8, Register> gpr28;
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BitField<39, 8, Register> gpr39;
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BitField<39, 8, Register> gpr39;
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BitField<48, 16, u64> opcode;
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BitField<48, 16, u64> opcode;
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@ -907,10 +907,6 @@ private:
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regs.SetRegisterToFloat(instr.gpr0, 0, "inversesqrt(" + op_a + ')', 1, 1,
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regs.SetRegisterToFloat(instr.gpr0, 0, "inversesqrt(" + op_a + ')', 1, 1,
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instr.alu.saturate_d);
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instr.alu.saturate_d);
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break;
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break;
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case SubOp::Min:
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regs.SetRegisterToFloat(instr.gpr0, 0, "min(" + op_a + "," + op_b + ')', 1, 1,
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instr.alu.saturate_d);
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break;
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default:
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default:
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NGLOG_CRITICAL(HW_GPU, "Unhandled MUFU sub op: {0:x}",
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NGLOG_CRITICAL(HW_GPU, "Unhandled MUFU sub op: {0:x}",
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static_cast<unsigned>(instr.sub_op.Value()));
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static_cast<unsigned>(instr.sub_op.Value()));
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