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GPU: Added register definitions for the vertex buffer base element.
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066d6184d4
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@ -455,7 +455,11 @@ public:
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u32 enable[NumRenderTargets];
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u32 enable[NumRenderTargets];
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} blend;
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} blend;
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INSERT_PADDING_WORDS(0x77);
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INSERT_PADDING_WORDS(0x2D);
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u32 vb_element_base;
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INSERT_PADDING_WORDS(0x49);
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struct {
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struct {
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u32 tsc_address_high;
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u32 tsc_address_high;
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@ -745,6 +749,7 @@ ASSERT_REG_POSITION(vertex_attrib_format[0], 0x458);
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ASSERT_REG_POSITION(rt_control, 0x487);
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ASSERT_REG_POSITION(rt_control, 0x487);
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ASSERT_REG_POSITION(independent_blend_enable, 0x4B9);
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ASSERT_REG_POSITION(independent_blend_enable, 0x4B9);
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ASSERT_REG_POSITION(blend, 0x4CF);
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ASSERT_REG_POSITION(blend, 0x4CF);
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ASSERT_REG_POSITION(vb_element_base, 0x50D);
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ASSERT_REG_POSITION(tsc, 0x557);
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ASSERT_REG_POSITION(tsc, 0x557);
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ASSERT_REG_POSITION(tic, 0x55D);
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ASSERT_REG_POSITION(tic, 0x55D);
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ASSERT_REG_POSITION(code_address, 0x582);
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ASSERT_REG_POSITION(code_address, 0x582);
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