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gl_shader_decompiler: Improve IPA for Pass mode with Position attribute.
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@ -230,6 +230,8 @@ enum class TextureType : u64 {
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TextureCube = 3,
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TextureCube = 3,
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};
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};
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enum class IpaMode : u64 { Pass = 0, None = 1, Constant = 2, Sc = 3 };
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union Instruction {
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union Instruction {
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Instruction& operator=(const Instruction& instr) {
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Instruction& operator=(const Instruction& instr) {
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value = instr.value;
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value = instr.value;
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@ -312,6 +314,10 @@ union Instruction {
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}
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}
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} alu;
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} alu;
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union {
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BitField<54, 3, IpaMode> mode;
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} ipa;
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union {
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union {
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BitField<48, 1, u64> negate_b;
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BitField<48, 1, u64> negate_b;
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} fmul;
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} fmul;
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@ -2039,7 +2039,39 @@ private:
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}
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}
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case OpCode::Id::IPA: {
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case OpCode::Id::IPA: {
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const auto& attribute = instr.attribute.fmt28;
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const auto& attribute = instr.attribute.fmt28;
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regs.SetRegisterToInputAttibute(instr.gpr0, attribute.element, attribute.index);
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const auto& reg = instr.gpr0;
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switch (instr.ipa.mode) {
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case Tegra::Shader::IpaMode::Pass:
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if (stage == Maxwell3D::Regs::ShaderStage::Fragment &&
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attribute.index == Attribute::Index::Position) {
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switch (attribute.element) {
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case 0:
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shader.AddLine(regs.GetRegisterAsFloat(reg) + " = gl_FragCoord.x;");
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break;
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case 1:
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shader.AddLine(regs.GetRegisterAsFloat(reg) + " = gl_FragCoord.y;");
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break;
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case 2:
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shader.AddLine(regs.GetRegisterAsFloat(reg) + " = gl_FragCoord.z;");
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break;
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case 3:
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shader.AddLine(regs.GetRegisterAsFloat(reg) + " = 1.0;");
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break;
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}
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} else {
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regs.SetRegisterToInputAttibute(reg, attribute.element, attribute.index);
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}
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break;
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case Tegra::Shader::IpaMode::None:
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regs.SetRegisterToInputAttibute(reg, attribute.element, attribute.index);
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break;
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default:
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LOG_CRITICAL(HW_GPU, "Unhandled IPA mode: {}",
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static_cast<u32>(instr.ipa.mode.Value()));
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UNREACHABLE();
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regs.SetRegisterToInputAttibute(reg, attribute.element, attribute.index);
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}
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break;
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break;
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}
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}
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case OpCode::Id::SSY: {
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case OpCode::Id::SSY: {
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