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gl_shader_decompiler: Improve IPA for Pass mode with Position attribute.

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This commit is contained in:
bunnei 2018-08-29 00:37:29 -04:00
parent 4d7e1662c8
commit b1ccd88434
2 changed files with 39 additions and 1 deletions
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6
src/video_core/engines/shader_bytecode.h
View file

@ -230,6 +230,8 @@ enum class TextureType : u64 {
TextureCube = 3,
};
enum class IpaMode : u64 { Pass = 0, None = 1, Constant = 2, Sc = 3 };
union Instruction {
Instruction& operator=(const Instruction& instr) {
value = instr.value;
@ -312,6 +314,10 @@ union Instruction {
}
} alu;
union {
BitField<54, 3, IpaMode> mode;
} ipa;
union {
BitField<48, 1, u64> negate_b;
} fmul;

34
src/video_core/renderer_opengl/gl_shader_decompiler.cpp
View file

@ -2039,7 +2039,39 @@ private:
}
case OpCode::Id::IPA: {
const auto& attribute = instr.attribute.fmt28;
regs.SetRegisterToInputAttibute(instr.gpr0, attribute.element, attribute.index);
const auto& reg = instr.gpr0;
switch (instr.ipa.mode) {
case Tegra::Shader::IpaMode::Pass:
if (stage == Maxwell3D::Regs::ShaderStage::Fragment &&
attribute.index == Attribute::Index::Position) {
switch (attribute.element) {
case 0:
shader.AddLine(regs.GetRegisterAsFloat(reg) + " = gl_FragCoord.x;");
break;
case 1:
shader.AddLine(regs.GetRegisterAsFloat(reg) + " = gl_FragCoord.y;");
break;
case 2:
shader.AddLine(regs.GetRegisterAsFloat(reg) + " = gl_FragCoord.z;");
break;
case 3:
shader.AddLine(regs.GetRegisterAsFloat(reg) + " = 1.0;");
break;
}
} else {
regs.SetRegisterToInputAttibute(reg, attribute.element, attribute.index);
}
break;
case Tegra::Shader::IpaMode::None:
regs.SetRegisterToInputAttibute(reg, attribute.element, attribute.index);
break;
default:
LOG_CRITICAL(HW_GPU, "Unhandled IPA mode: {}",
static_cast<u32>(instr.ipa.mode.Value()));
UNREACHABLE();
regs.SetRegisterToInputAttibute(reg, attribute.element, attribute.index);
}
break;
}
case OpCode::Id::SSY: {