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Added better asserts to IPA, Renamed IPA modes to match mesa
IpaMode is changed to IpaInterpMode
IpaMode is suppose to be 2 bits not 3
Added IpaSampleMode
Added Saturate
Renamed modes based on
d27c791891/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp (L2530)
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@ -243,7 +243,8 @@ enum class TextureType : u64 {
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TextureCube = 3,
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};
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enum class IpaMode : u64 { Pass = 0, None = 1, Constant = 2, Sc = 3 };
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enum class IpaInterpMode : u64 { Linear = 0, Perspective = 1, Flat = 2, Sc = 3 };
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enum class IpaSampleMode : u64 { Default = 0, Centroid = 1, Offset = 2 };
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union Instruction {
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Instruction& operator=(const Instruction& instr) {
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@ -328,7 +329,9 @@ union Instruction {
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} alu;
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union {
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BitField<54, 3, IpaMode> mode;
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BitField<51, 1, u64> saturate;
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BitField<52, 2, IpaSampleMode> sample_mode;
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BitField<54, 2, IpaInterpMode> interp_mode;
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} ipa;
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union {
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@ -2110,8 +2110,12 @@ private:
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case OpCode::Id::IPA: {
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const auto& attribute = instr.attribute.fmt28;
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const auto& reg = instr.gpr0;
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switch (instr.ipa.mode) {
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case Tegra::Shader::IpaMode::Pass:
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ASSERT_MSG(instr.ipa.sample_mode == Tegra::Shader::IpaSampleMode::Default,
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"Unhandled IPA sample mode: {}",
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static_cast<u32>(instr.ipa.sample_mode.Value()));
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ASSERT_MSG(instr.ipa.saturate == 0, "IPA saturate not implemented");
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switch (instr.ipa.interp_mode) {
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case Tegra::Shader::IpaInterpMode::Linear:
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if (stage == Maxwell3D::Regs::ShaderStage::Fragment &&
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attribute.index == Attribute::Index::Position) {
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switch (attribute.element) {
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@ -2132,12 +2136,12 @@ private:
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regs.SetRegisterToInputAttibute(reg, attribute.element, attribute.index);
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}
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break;
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case Tegra::Shader::IpaMode::None:
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case Tegra::Shader::IpaInterpMode::Perspective:
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regs.SetRegisterToInputAttibute(reg, attribute.element, attribute.index);
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break;
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default:
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LOG_CRITICAL(HW_GPU, "Unhandled IPA mode: {}",
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static_cast<u32>(instr.ipa.mode.Value()));
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static_cast<u32>(instr.ipa.interp_mode.Value()));
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UNREACHABLE();
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regs.SetRegisterToInputAttibute(reg, attribute.element, attribute.index);
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}
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