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arm_dyncom_interpreter: Add specialized GetAddressingOpLoadStoreT func

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This allows us to get the addressing operation for STRT, LDRT, STRBT,
and LDRBT. We do this so that translation functions don't need to
see the addressing ops directly.
This commit is contained in:
archshift 2016-06-10 18:45:48 -07:00
parent eac4c016cb
commit 765eef3319
2 changed files with 19 additions and 39 deletions
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15
src/core/arm/dyncom/arm_dyncom_interpreter.cpp
View file

@ -753,6 +753,21 @@ static get_addr_fp_t GetAddressingOp(unsigned int inst) {
return nullptr;
}
// Specialized for LDRT, LDRBT, STRT, and STRBT, which have specific addressing mode requirements
get_addr_fp_t GetAddressingOpLoadStoreT(unsigned int inst) {
if (BITS(inst, 25, 27) == 2) {
return LnSWoUB(ImmediatePostIndexed);
} else if (BITS(inst, 25, 27) == 3) {
return LnSWoUB(ScaledRegisterPostIndexed);
}
// Reaching this would indicate the thumb version
// of this instruction, however the 3DS CPU doesn't
// support this variant (the 3DS CPU is only ARMv6K,
// while this variant is added in ARMv6T2).
// So it's sufficient for citra to not implement this.
return nullptr;
}
typedef ARM_INST_PTR (*transop_fp_t)(unsigned int, int);
#include "arm_dyncom_trans.inc"

43
src/core/arm/dyncom/arm_dyncom_trans.inc
View file

@ -420,13 +420,7 @@ static ARM_INST_PTR INTERPRETER_TRANSLATE(ldrbt)(unsigned int inst, int index)
inst_base->br = TransExtData::NON_BRANCH;
inst_cream->inst = inst;
if (BITS(inst, 25, 27) == 2) {
inst_cream->get_addr = LnSWoUB(ImmediatePostIndexed);
} else if (BITS(inst, 25, 27) == 3) {
inst_cream->get_addr = LnSWoUB(ScaledRegisterPostIndexed);
} else {
DEBUG_MSG;
}
inst_cream->get_addr = GetAddressingOpLoadStoreT(inst);
return inst_base;
}
@ -522,18 +516,7 @@ static ARM_INST_PTR INTERPRETER_TRANSLATE(ldrt)(unsigned int inst, int index)
inst_base->br = TransExtData::NON_BRANCH;
inst_cream->inst = inst;
if (BITS(inst, 25, 27) == 2) {
inst_cream->get_addr = LnSWoUB(ImmediatePostIndexed);
} else if (BITS(inst, 25, 27) == 3) {
inst_cream->get_addr = LnSWoUB(ScaledRegisterPostIndexed);
} else {
// Reaching this would indicate the thumb version
// of this instruction, however the 3DS CPU doesn't
// support this variant (the 3DS CPU is only ARMv6K,
// while this variant is added in ARMv6T2).
// So it's sufficient for citra to not implement this.
DEBUG_MSG;
}
inst_cream->get_addr = GetAddressingOpLoadStoreT(inst);
if (BITS(inst, 12, 15) == 15) {
inst_base->br = TransExtData::INDIRECT_BRANCH;
@ -1424,14 +1407,7 @@ static ARM_INST_PTR INTERPRETER_TRANSLATE(strbt)(unsigned int inst, int index)
inst_base->br = TransExtData::NON_BRANCH;
inst_cream->inst = inst;
if (BITS(inst, 25, 27) == 2) {
inst_cream->get_addr = LnSWoUB(ImmediatePostIndexed);
} else if (BITS(inst, 25, 27) == 3) {
inst_cream->get_addr = LnSWoUB(ScaledRegisterPostIndexed);
} else {
DEBUG_MSG;
}
inst_cream->get_addr = GetAddressingOpLoadStoreT(inst);
return inst_base;
}
@ -1499,18 +1475,7 @@ static ARM_INST_PTR INTERPRETER_TRANSLATE(strt)(unsigned int inst, int index)
inst_base->br = TransExtData::NON_BRANCH;
inst_cream->inst = inst;
if (BITS(inst, 25, 27) == 2) {
inst_cream->get_addr = LnSWoUB(ImmediatePostIndexed);
} else if (BITS(inst, 25, 27) == 3) {
inst_cream->get_addr = LnSWoUB(ScaledRegisterPostIndexed);
} else {
// Reaching this would indicate the thumb version
// of this instruction, however the 3DS CPU doesn't
// support this variant (the 3DS CPU is only ARMv6K,
// while this variant is added in ARMv6T2).
// So it's sufficient for citra to not implement this.
DEBUG_MSG;
}
inst_cream->get_addr = GetAddressingOpLoadStoreT(inst);
return inst_base;
}