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Merge pull request #422 from lioncash/bxj

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dyncom: Partially emulate BXJ
This commit is contained in:
bunnei 2015-01-05 16:36:29 -05:00
parent 4828d0b7af f75def619c
commit 6fad32ea98
1 changed files with 25 additions and 8 deletions
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25
src/core/arm/dyncom/arm_dyncom_interpreter.cpp
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@ -1427,7 +1427,11 @@ ARM_INST_PTR INTERPRETER_TRANSLATE(bx)(unsigned int inst, int index)
return inst_base;
}
ARM_INST_PTR INTERPRETER_TRANSLATE(bxj)(unsigned int inst, int index) { UNIMPLEMENTED_INSTRUCTION("BXJ"); }
ARM_INST_PTR INTERPRETER_TRANSLATE(bxj)(unsigned int inst, int index)
{
return INTERPRETER_TRANSLATE(bx)(inst, index);
}
ARM_INST_PTR INTERPRETER_TRANSLATE(cdp)(unsigned int inst, int index){
arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(cdp_inst));
cdp_inst *inst_cream = (cdp_inst *)inst_base->component;
@ -4129,22 +4133,35 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
INC_PC(sizeof(blx_inst));
goto DISPATCH;
}
BX_INST:
BXJ_INST:
{
bx_inst *inst_cream = (bx_inst *)inst_base->component;
if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
// Note that only the 'fail' case of BXJ is emulated. This is because
// the facilities for Jazelle emulation are not implemented.
//
// According to the ARM documentation on BXJ, if setting the J bit in the APSR
// fails, then BXJ functions identically like a regular BX instruction.
//
// This is sufficient for citra, as the CPU for the 3DS does not implement Jazelle.
if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
bx_inst* const inst_cream = (bx_inst*)inst_base->component;
if (inst_cream->Rm == 15)
LOG_WARNING(Core_ARM11, "BX at pc %x: use of Rm = R15 is discouraged", cpu->Reg[15]);
cpu->TFlag = cpu->Reg[inst_cream->Rm] & 0x1;
cpu->Reg[15] = cpu->Reg[inst_cream->Rm] & 0xfffffffe;
INC_PC(sizeof(bx_inst));
goto DISPATCH;
}
cpu->Reg[15] += GET_INST_SIZE(cpu);
INC_PC(sizeof(bx_inst));
goto DISPATCH;
}
BXJ_INST:
CDP_INST:
{
cdp_inst *inst_cream = (cdp_inst *)inst_base->component;