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Shader_IR: Implement ICMP.
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@ -933,6 +933,11 @@ union Instruction {
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BitField<49, 3, PredCondition> cond;
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} isetp;
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union {
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BitField<48, 1, u64> is_signed;
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BitField<49, 3, PredCondition> cond;
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} icmp;
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union {
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BitField<0, 3, u64> pred0;
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BitField<3, 3, u64> pred3;
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@ -1628,6 +1633,9 @@ public:
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SEL_C,
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SEL_R,
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SEL_IMM,
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ICMP_RC,
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ICMP_R,
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ICMP_CR,
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MUFU, // Multi-Function Operator
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RRO_C, // Range Reduction Operator
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RRO_R,
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@ -1892,6 +1900,9 @@ private:
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INST("0100110010100---", Id::SEL_C, Type::ArithmeticInteger, "SEL_C"),
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INST("0101110010100---", Id::SEL_R, Type::ArithmeticInteger, "SEL_R"),
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INST("0011100-10100---", Id::SEL_IMM, Type::ArithmeticInteger, "SEL_IMM"),
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INST("010100110100----", Id::ICMP_RC, Type::ArithmeticInteger, "ICMP_RC"),
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INST("010110110100----", Id::ICMP_R, Type::ArithmeticInteger, "ICMP_R"),
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INST("010010110100----", Id::ICMP_CR, Type::ArithmeticInteger, "ICMP_CR"),
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INST("0101101111011---", Id::LEA_R2, Type::ArithmeticInteger, "LEA_R2"),
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INST("0101101111010---", Id::LEA_R1, Type::ArithmeticInteger, "LEA_R1"),
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INST("001101101101----", Id::LEA_IMM, Type::ArithmeticInteger, "LEA_IMM"),
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@ -138,6 +138,32 @@ u32 ShaderIR::DecodeArithmeticInteger(NodeBlock& bb, u32 pc) {
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SetRegister(bb, instr.gpr0, value);
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break;
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}
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case OpCode::Id::ICMP_CR:
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case OpCode::Id::ICMP_R:
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case OpCode::Id::ICMP_RC: {
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UNIMPLEMENTED_IF(instr.icmp.is_signed != 0);
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const Node zero = Immediate(0);
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const auto [op_a, op_b] = [&]() -> std::tuple<Node, Node> {
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switch (opcode->get().GetId()) {
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case OpCode::Id::ICMP_CR:
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return {GetConstBuffer(instr.cbuf34.index, instr.cbuf34.offset),
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GetRegister(instr.gpr39)};
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case OpCode::Id::ICMP_R:
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return {GetRegister(instr.gpr20), GetRegister(instr.gpr39)};
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case OpCode::Id::ICMP_RC:
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return {GetRegister(instr.gpr39),
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GetConstBuffer(instr.cbuf34.index, instr.cbuf34.offset)};
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default:
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UNIMPLEMENTED();
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return {zero, zero};
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}
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}();
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const Node test = GetRegister(instr.gpr8);
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const Node comparison = GetPredicateComparisonInteger(instr.icmp.cond, false, test, zero);
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SetRegister(bb, instr.gpr0, Operation(OperationCode::Select, comparison, op_a, op_b));
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break;
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}
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case OpCode::Id::LOP_C:
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case OpCode::Id::LOP_R:
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case OpCode::Id::LOP_IMM: {
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