mirror of
https://git.h3cjp.net/H3cJP/yuzu.git
synced 2024-12-15 07:15:01 +00:00
shader_ir: Rename BasicBlock to NodeBlock
It's not always used as a basic block. Rename it for consistency.
This commit is contained in:
parent
6a6fabea58
commit
42b75e8be8
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@ -171,7 +171,7 @@ public:
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code.AddLine(fmt::format("case 0x{:x}u: {{", address));
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++code.scope;
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VisitBasicBlock(bb);
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VisitBlock(bb);
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--code.scope;
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code.AddLine('}');
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@ -424,7 +424,7 @@ private:
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code.AddNewLine();
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}
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void VisitBasicBlock(const BasicBlock& bb) {
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void VisitBlock(const NodeBlock& bb) {
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for (const Node node : bb) {
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if (const std::string expr = Visit(node); !expr.empty()) {
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code.AddLine(expr);
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@ -576,7 +576,7 @@ private:
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code.AddLine("if (" + Visit(conditional->GetCondition()) + ") {");
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++code.scope;
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VisitBasicBlock(conditional->GetCode());
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VisitBlock(conditional->GetCode());
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--code.scope;
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code.AddLine('}');
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@ -121,15 +121,15 @@ ExitMethod ShaderIR::Scan(u32 begin, u32 end, std::set<u32>& labels) {
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return exit_method = ExitMethod::AlwaysReturn;
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}
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BasicBlock ShaderIR::DecodeRange(u32 begin, u32 end) {
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BasicBlock basic_block;
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NodeBlock ShaderIR::DecodeRange(u32 begin, u32 end) {
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NodeBlock basic_block;
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for (u32 pc = begin; pc < (begin > end ? MAX_PROGRAM_LENGTH : end);) {
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pc = DecodeInstr(basic_block, pc);
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}
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return basic_block;
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}
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u32 ShaderIR::DecodeInstr(BasicBlock& bb, u32 pc) {
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u32 ShaderIR::DecodeInstr(NodeBlock& bb, u32 pc) {
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// Ignore sched instructions when generating code.
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if (IsSchedInstruction(pc, main_offset)) {
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return pc + 1;
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@ -151,33 +151,32 @@ u32 ShaderIR::DecodeInstr(BasicBlock& bb, u32 pc) {
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UNIMPLEMENTED_IF_MSG(instr.pred.full_pred == Pred::NeverExecute,
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"NeverExecute predicate not implemented");
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static const std::map<OpCode::Type, u32 (ShaderIR::*)(BasicBlock&, u32)>
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decoders = {
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{OpCode::Type::Arithmetic, &ShaderIR::DecodeArithmetic},
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{OpCode::Type::ArithmeticImmediate, &ShaderIR::DecodeArithmeticImmediate},
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{OpCode::Type::Bfe, &ShaderIR::DecodeBfe},
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{OpCode::Type::Bfi, &ShaderIR::DecodeBfi},
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{OpCode::Type::Shift, &ShaderIR::DecodeShift},
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{OpCode::Type::ArithmeticInteger, &ShaderIR::DecodeArithmeticInteger},
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{OpCode::Type::ArithmeticIntegerImmediate, &ShaderIR::DecodeArithmeticIntegerImmediate},
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{OpCode::Type::ArithmeticHalf, &ShaderIR::DecodeArithmeticHalf},
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{OpCode::Type::ArithmeticHalfImmediate, &ShaderIR::DecodeArithmeticHalfImmediate},
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{OpCode::Type::Ffma, &ShaderIR::DecodeFfma},
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{OpCode::Type::Hfma2, &ShaderIR::DecodeHfma2},
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{OpCode::Type::Conversion, &ShaderIR::DecodeConversion},
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{OpCode::Type::Memory, &ShaderIR::DecodeMemory},
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{OpCode::Type::FloatSetPredicate, &ShaderIR::DecodeFloatSetPredicate},
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{OpCode::Type::IntegerSetPredicate, &ShaderIR::DecodeIntegerSetPredicate},
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{OpCode::Type::HalfSetPredicate, &ShaderIR::DecodeHalfSetPredicate},
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{OpCode::Type::PredicateSetRegister, &ShaderIR::DecodePredicateSetRegister},
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{OpCode::Type::PredicateSetPredicate, &ShaderIR::DecodePredicateSetPredicate},
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{OpCode::Type::RegisterSetPredicate, &ShaderIR::DecodeRegisterSetPredicate},
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{OpCode::Type::FloatSet, &ShaderIR::DecodeFloatSet},
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{OpCode::Type::IntegerSet, &ShaderIR::DecodeIntegerSet},
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{OpCode::Type::HalfSet, &ShaderIR::DecodeHalfSet},
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{OpCode::Type::Video, &ShaderIR::DecodeVideo},
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{OpCode::Type::Xmad, &ShaderIR::DecodeXmad},
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};
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static const std::map<OpCode::Type, u32 (ShaderIR::*)(NodeBlock&, u32)> decoders = {
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{OpCode::Type::Arithmetic, &ShaderIR::DecodeArithmetic},
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{OpCode::Type::ArithmeticImmediate, &ShaderIR::DecodeArithmeticImmediate},
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{OpCode::Type::Bfe, &ShaderIR::DecodeBfe},
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{OpCode::Type::Bfi, &ShaderIR::DecodeBfi},
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{OpCode::Type::Shift, &ShaderIR::DecodeShift},
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{OpCode::Type::ArithmeticInteger, &ShaderIR::DecodeArithmeticInteger},
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{OpCode::Type::ArithmeticIntegerImmediate, &ShaderIR::DecodeArithmeticIntegerImmediate},
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{OpCode::Type::ArithmeticHalf, &ShaderIR::DecodeArithmeticHalf},
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{OpCode::Type::ArithmeticHalfImmediate, &ShaderIR::DecodeArithmeticHalfImmediate},
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{OpCode::Type::Ffma, &ShaderIR::DecodeFfma},
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{OpCode::Type::Hfma2, &ShaderIR::DecodeHfma2},
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{OpCode::Type::Conversion, &ShaderIR::DecodeConversion},
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{OpCode::Type::Memory, &ShaderIR::DecodeMemory},
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{OpCode::Type::FloatSetPredicate, &ShaderIR::DecodeFloatSetPredicate},
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{OpCode::Type::IntegerSetPredicate, &ShaderIR::DecodeIntegerSetPredicate},
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{OpCode::Type::HalfSetPredicate, &ShaderIR::DecodeHalfSetPredicate},
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{OpCode::Type::PredicateSetRegister, &ShaderIR::DecodePredicateSetRegister},
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{OpCode::Type::PredicateSetPredicate, &ShaderIR::DecodePredicateSetPredicate},
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{OpCode::Type::RegisterSetPredicate, &ShaderIR::DecodeRegisterSetPredicate},
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{OpCode::Type::FloatSet, &ShaderIR::DecodeFloatSet},
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{OpCode::Type::IntegerSet, &ShaderIR::DecodeIntegerSet},
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{OpCode::Type::HalfSet, &ShaderIR::DecodeHalfSet},
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{OpCode::Type::Video, &ShaderIR::DecodeVideo},
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{OpCode::Type::Xmad, &ShaderIR::DecodeXmad},
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};
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std::vector<Node> tmp_block;
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if (const auto decoder = decoders.find(opcode->get().GetType()); decoder != decoders.end()) {
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@ -13,7 +13,7 @@ using Tegra::Shader::Instruction;
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using Tegra::Shader::OpCode;
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using Tegra::Shader::SubOp;
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u32 ShaderIR::DecodeArithmetic(BasicBlock& bb, u32 pc) {
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u32 ShaderIR::DecodeArithmetic(NodeBlock& bb, u32 pc) {
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const Instruction instr = {program_code[pc]};
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const auto opcode = OpCode::Decode(instr);
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@ -12,7 +12,7 @@ namespace VideoCommon::Shader {
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using Tegra::Shader::Instruction;
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using Tegra::Shader::OpCode;
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u32 ShaderIR::DecodeArithmeticHalf(BasicBlock& bb, u32 pc) {
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u32 ShaderIR::DecodeArithmeticHalf(NodeBlock& bb, u32 pc) {
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const Instruction instr = {program_code[pc]};
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const auto opcode = OpCode::Decode(instr);
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@ -12,7 +12,7 @@ namespace VideoCommon::Shader {
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using Tegra::Shader::Instruction;
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using Tegra::Shader::OpCode;
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u32 ShaderIR::DecodeArithmeticHalfImmediate(BasicBlock& bb, u32 pc) {
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u32 ShaderIR::DecodeArithmeticHalfImmediate(NodeBlock& bb, u32 pc) {
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const Instruction instr = {program_code[pc]};
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const auto opcode = OpCode::Decode(instr);
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@ -12,7 +12,7 @@ namespace VideoCommon::Shader {
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using Tegra::Shader::Instruction;
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using Tegra::Shader::OpCode;
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u32 ShaderIR::DecodeArithmeticImmediate(BasicBlock& bb, u32 pc) {
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u32 ShaderIR::DecodeArithmeticImmediate(NodeBlock& bb, u32 pc) {
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const Instruction instr = {program_code[pc]};
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const auto opcode = OpCode::Decode(instr);
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@ -15,7 +15,7 @@ using Tegra::Shader::OpCode;
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using Tegra::Shader::Pred;
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using Tegra::Shader::Register;
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u32 ShaderIR::DecodeArithmeticInteger(BasicBlock& bb, u32 pc) {
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u32 ShaderIR::DecodeArithmeticInteger(NodeBlock& bb, u32 pc) {
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const Instruction instr = {program_code[pc]};
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const auto opcode = OpCode::Decode(instr);
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@ -242,7 +242,7 @@ u32 ShaderIR::DecodeArithmeticInteger(BasicBlock& bb, u32 pc) {
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return pc;
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}
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void ShaderIR::WriteLop3Instruction(BasicBlock& bb, Register dest, Node op_a, Node op_b, Node op_c,
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void ShaderIR::WriteLop3Instruction(NodeBlock& bb, Register dest, Node op_a, Node op_b, Node op_c,
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Node imm_lut, bool sets_cc) {
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constexpr u32 lop_iterations = 32;
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const Node one = Immediate(1);
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@ -16,7 +16,7 @@ using Tegra::Shader::Pred;
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using Tegra::Shader::PredicateResultMode;
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using Tegra::Shader::Register;
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u32 ShaderIR::DecodeArithmeticIntegerImmediate(BasicBlock& bb, u32 pc) {
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u32 ShaderIR::DecodeArithmeticIntegerImmediate(NodeBlock& bb, u32 pc) {
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const Instruction instr = {program_code[pc]};
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const auto opcode = OpCode::Decode(instr);
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@ -54,9 +54,9 @@ u32 ShaderIR::DecodeArithmeticIntegerImmediate(BasicBlock& bb, u32 pc) {
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return pc;
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}
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void ShaderIR::WriteLogicOperation(BasicBlock& bb, Register dest, LogicOperation logic_op,
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Node op_a, Node op_b, PredicateResultMode predicate_mode,
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Pred predicate, bool sets_cc) {
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void ShaderIR::WriteLogicOperation(NodeBlock& bb, Register dest, LogicOperation logic_op, Node op_a,
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Node op_b, PredicateResultMode predicate_mode, Pred predicate,
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bool sets_cc) {
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const Node result = [&]() {
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switch (logic_op) {
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case LogicOperation::And:
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@ -12,7 +12,7 @@ namespace VideoCommon::Shader {
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using Tegra::Shader::Instruction;
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using Tegra::Shader::OpCode;
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u32 ShaderIR::DecodeBfe(BasicBlock& bb, u32 pc) {
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u32 ShaderIR::DecodeBfe(NodeBlock& bb, u32 pc) {
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const Instruction instr = {program_code[pc]};
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const auto opcode = OpCode::Decode(instr);
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@ -12,7 +12,7 @@ namespace VideoCommon::Shader {
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using Tegra::Shader::Instruction;
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using Tegra::Shader::OpCode;
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u32 ShaderIR::DecodeBfi(BasicBlock& bb, u32 pc) {
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u32 ShaderIR::DecodeBfi(NodeBlock& bb, u32 pc) {
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const Instruction instr = {program_code[pc]};
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const auto opcode = OpCode::Decode(instr);
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@ -13,7 +13,7 @@ using Tegra::Shader::Instruction;
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using Tegra::Shader::OpCode;
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using Tegra::Shader::Register;
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u32 ShaderIR::DecodeConversion(BasicBlock& bb, u32 pc) {
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u32 ShaderIR::DecodeConversion(NodeBlock& bb, u32 pc) {
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const Instruction instr = {program_code[pc]};
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const auto opcode = OpCode::Decode(instr);
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@ -12,7 +12,7 @@ namespace VideoCommon::Shader {
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using Tegra::Shader::Instruction;
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using Tegra::Shader::OpCode;
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u32 ShaderIR::DecodeFfma(BasicBlock& bb, u32 pc) {
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u32 ShaderIR::DecodeFfma(NodeBlock& bb, u32 pc) {
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const Instruction instr = {program_code[pc]};
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const auto opcode = OpCode::Decode(instr);
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@ -12,7 +12,7 @@ namespace VideoCommon::Shader {
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using Tegra::Shader::Instruction;
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using Tegra::Shader::OpCode;
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u32 ShaderIR::DecodeFloatSet(BasicBlock& bb, u32 pc) {
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u32 ShaderIR::DecodeFloatSet(NodeBlock& bb, u32 pc) {
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const Instruction instr = {program_code[pc]};
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const auto opcode = OpCode::Decode(instr);
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@ -13,7 +13,7 @@ using Tegra::Shader::Instruction;
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using Tegra::Shader::OpCode;
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using Tegra::Shader::Pred;
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u32 ShaderIR::DecodeFloatSetPredicate(BasicBlock& bb, u32 pc) {
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u32 ShaderIR::DecodeFloatSetPredicate(NodeBlock& bb, u32 pc) {
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const Instruction instr = {program_code[pc]};
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const auto opcode = OpCode::Decode(instr);
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@ -14,7 +14,7 @@ namespace VideoCommon::Shader {
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using Tegra::Shader::Instruction;
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using Tegra::Shader::OpCode;
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u32 ShaderIR::DecodeHalfSet(BasicBlock& bb, u32 pc) {
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u32 ShaderIR::DecodeHalfSet(NodeBlock& bb, u32 pc) {
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const Instruction instr = {program_code[pc]};
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const auto opcode = OpCode::Decode(instr);
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@ -13,7 +13,7 @@ using Tegra::Shader::Instruction;
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using Tegra::Shader::OpCode;
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using Tegra::Shader::Pred;
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u32 ShaderIR::DecodeHalfSetPredicate(BasicBlock& bb, u32 pc) {
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u32 ShaderIR::DecodeHalfSetPredicate(NodeBlock& bb, u32 pc) {
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const Instruction instr = {program_code[pc]};
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const auto opcode = OpCode::Decode(instr);
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@ -16,7 +16,7 @@ using Tegra::Shader::HalfType;
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using Tegra::Shader::Instruction;
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using Tegra::Shader::OpCode;
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u32 ShaderIR::DecodeHfma2(BasicBlock& bb, u32 pc) {
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u32 ShaderIR::DecodeHfma2(NodeBlock& bb, u32 pc) {
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const Instruction instr = {program_code[pc]};
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const auto opcode = OpCode::Decode(instr);
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@ -12,7 +12,7 @@ namespace VideoCommon::Shader {
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using Tegra::Shader::Instruction;
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using Tegra::Shader::OpCode;
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u32 ShaderIR::DecodeIntegerSet(BasicBlock& bb, u32 pc) {
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u32 ShaderIR::DecodeIntegerSet(NodeBlock& bb, u32 pc) {
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const Instruction instr = {program_code[pc]};
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const auto opcode = OpCode::Decode(instr);
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@ -13,7 +13,7 @@ using Tegra::Shader::Instruction;
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using Tegra::Shader::OpCode;
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using Tegra::Shader::Pred;
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u32 ShaderIR::DecodeIntegerSetPredicate(BasicBlock& bb, u32 pc) {
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u32 ShaderIR::DecodeIntegerSetPredicate(NodeBlock& bb, u32 pc) {
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const Instruction instr = {program_code[pc]};
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const auto opcode = OpCode::Decode(instr);
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@ -36,7 +36,7 @@ static std::size_t GetCoordCount(TextureType texture_type) {
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}
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}
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u32 ShaderIR::DecodeMemory(BasicBlock& bb, u32 pc) {
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u32 ShaderIR::DecodeMemory(NodeBlock& bb, u32 pc) {
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const Instruction instr = {program_code[pc]};
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const auto opcode = OpCode::Decode(instr);
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@ -431,8 +431,7 @@ const Sampler& ShaderIR::GetSampler(const Tegra::Shader::Sampler& sampler, Textu
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return *used_samplers.emplace(entry).first;
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}
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void ShaderIR::WriteTexInstructionFloat(BasicBlock& bb, Instruction instr,
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const Node4& components) {
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void ShaderIR::WriteTexInstructionFloat(NodeBlock& bb, Instruction instr, const Node4& components) {
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u32 dest_elem = 0;
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for (u32 elem = 0; elem < 4; ++elem) {
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if (!instr.tex.IsComponentEnabled(elem)) {
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}
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}
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void ShaderIR::WriteTexsInstructionFloat(BasicBlock& bb, Instruction instr,
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void ShaderIR::WriteTexsInstructionFloat(NodeBlock& bb, Instruction instr,
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const Node4& components) {
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// TEXS has two destination registers and a swizzle. The first two elements in the swizzle
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// go into gpr0+0 and gpr0+1, and the rest goes into gpr28+0 and gpr28+1
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}
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}
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void ShaderIR::WriteTexsInstructionHalfFloat(BasicBlock& bb, Instruction instr,
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void ShaderIR::WriteTexsInstructionHalfFloat(NodeBlock& bb, Instruction instr,
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const Node4& components) {
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// TEXS.F16 destionation registers are packed in two registers in pairs (just like any half
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// float instruction).
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@ -14,7 +14,7 @@ using Tegra::Shader::Instruction;
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using Tegra::Shader::OpCode;
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using Tegra::Shader::Register;
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u32 ShaderIR::DecodeOther(BasicBlock& bb, u32 pc) {
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u32 ShaderIR::DecodeOther(NodeBlock& bb, u32 pc) {
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const Instruction instr = {program_code[pc]};
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const auto opcode = OpCode::Decode(instr);
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@ -13,7 +13,7 @@ using Tegra::Shader::Instruction;
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using Tegra::Shader::OpCode;
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using Tegra::Shader::Pred;
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u32 ShaderIR::DecodePredicateSetPredicate(BasicBlock& bb, u32 pc) {
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u32 ShaderIR::DecodePredicateSetPredicate(NodeBlock& bb, u32 pc) {
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const Instruction instr = {program_code[pc]};
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const auto opcode = OpCode::Decode(instr);
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@ -12,7 +12,7 @@ namespace VideoCommon::Shader {
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using Tegra::Shader::Instruction;
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using Tegra::Shader::OpCode;
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u32 ShaderIR::DecodePredicateSetRegister(BasicBlock& bb, u32 pc) {
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u32 ShaderIR::DecodePredicateSetRegister(NodeBlock& bb, u32 pc) {
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const Instruction instr = {program_code[pc]};
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const auto opcode = OpCode::Decode(instr);
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@ -12,7 +12,7 @@ namespace VideoCommon::Shader {
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using Tegra::Shader::Instruction;
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using Tegra::Shader::OpCode;
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u32 ShaderIR::DecodeRegisterSetPredicate(BasicBlock& bb, u32 pc) {
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u32 ShaderIR::DecodeRegisterSetPredicate(NodeBlock& bb, u32 pc) {
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const Instruction instr = {program_code[pc]};
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const auto opcode = OpCode::Decode(instr);
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@ -12,7 +12,7 @@ namespace VideoCommon::Shader {
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using Tegra::Shader::Instruction;
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using Tegra::Shader::OpCode;
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u32 ShaderIR::DecodeShift(BasicBlock& bb, u32 pc) {
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u32 ShaderIR::DecodeShift(NodeBlock& bb, u32 pc) {
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const Instruction instr = {program_code[pc]};
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const auto opcode = OpCode::Decode(instr);
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@ -15,7 +15,7 @@ using Tegra::Shader::Pred;
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using Tegra::Shader::VideoType;
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using Tegra::Shader::VmadShr;
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u32 ShaderIR::DecodeVideo(BasicBlock& bb, u32 pc) {
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u32 ShaderIR::DecodeVideo(NodeBlock& bb, u32 pc) {
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const Instruction instr = {program_code[pc]};
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||||
const auto opcode = OpCode::Decode(instr);
|
||||
|
||||
|
|
|
@ -12,7 +12,7 @@ namespace VideoCommon::Shader {
|
|||
using Tegra::Shader::Instruction;
|
||||
using Tegra::Shader::OpCode;
|
||||
|
||||
u32 ShaderIR::DecodeXmad(BasicBlock& bb, u32 pc) {
|
||||
u32 ShaderIR::DecodeXmad(NodeBlock& bb, u32 pc) {
|
||||
const Instruction instr = {program_code[pc]};
|
||||
const auto opcode = OpCode::Decode(instr);
|
||||
|
||||
|
|
|
@ -337,27 +337,27 @@ Node ShaderIR::GetConditionCode(Tegra::Shader::ConditionCode cc) {
|
|||
}
|
||||
}
|
||||
|
||||
void ShaderIR::SetRegister(BasicBlock& bb, Register dest, Node src) {
|
||||
void ShaderIR::SetRegister(NodeBlock& bb, Register dest, Node src) {
|
||||
bb.push_back(Operation(OperationCode::Assign, GetRegister(dest), src));
|
||||
}
|
||||
|
||||
void ShaderIR::SetPredicate(BasicBlock& bb, u64 dest, Node src) {
|
||||
void ShaderIR::SetPredicate(NodeBlock& bb, u64 dest, Node src) {
|
||||
bb.push_back(Operation(OperationCode::LogicalAssign, GetPredicate(dest), src));
|
||||
}
|
||||
|
||||
void ShaderIR::SetInternalFlag(BasicBlock& bb, InternalFlag flag, Node value) {
|
||||
void ShaderIR::SetInternalFlag(NodeBlock& bb, InternalFlag flag, Node value) {
|
||||
bb.push_back(Operation(OperationCode::LogicalAssign, GetInternalFlag(flag), value));
|
||||
}
|
||||
|
||||
void ShaderIR::SetLocalMemory(BasicBlock& bb, Node address, Node value) {
|
||||
void ShaderIR::SetLocalMemory(NodeBlock& bb, Node address, Node value) {
|
||||
bb.push_back(Operation(OperationCode::Assign, GetLocalMemory(address), value));
|
||||
}
|
||||
|
||||
void ShaderIR::SetTemporal(BasicBlock& bb, u32 id, Node value) {
|
||||
void ShaderIR::SetTemporal(NodeBlock& bb, u32 id, Node value) {
|
||||
SetRegister(bb, Register::ZeroIndex + 1 + id, value);
|
||||
}
|
||||
|
||||
void ShaderIR::SetInternalFlagsFromFloat(BasicBlock& bb, Node value, bool sets_cc) {
|
||||
void ShaderIR::SetInternalFlagsFromFloat(NodeBlock& bb, Node value, bool sets_cc) {
|
||||
if (!sets_cc) {
|
||||
return;
|
||||
}
|
||||
|
@ -366,7 +366,7 @@ void ShaderIR::SetInternalFlagsFromFloat(BasicBlock& bb, Node value, bool sets_c
|
|||
LOG_WARNING(HW_GPU, "Condition codes implementation is incomplete");
|
||||
}
|
||||
|
||||
void ShaderIR::SetInternalFlagsFromInteger(BasicBlock& bb, Node value, bool sets_cc) {
|
||||
void ShaderIR::SetInternalFlagsFromInteger(NodeBlock& bb, Node value, bool sets_cc) {
|
||||
if (!sets_cc) {
|
||||
return;
|
||||
}
|
||||
|
|
|
@ -39,7 +39,7 @@ using NodeData =
|
|||
PredicateNode, AbufNode, CbufNode, LmemNode, GmemNode, CommentNode>;
|
||||
using Node = const NodeData*;
|
||||
using Node4 = std::array<Node, 4>;
|
||||
using BasicBlock = std::vector<Node>;
|
||||
using NodeBlock = std::vector<Node>;
|
||||
|
||||
constexpr u32 MAX_PROGRAM_LENGTH = 0x1000;
|
||||
|
||||
|
@ -530,7 +530,7 @@ public:
|
|||
Decode();
|
||||
}
|
||||
|
||||
const std::map<u32, BasicBlock>& GetBasicBlocks() const {
|
||||
const std::map<u32, NodeBlock>& GetBasicBlocks() const {
|
||||
return basic_blocks;
|
||||
}
|
||||
|
||||
|
@ -581,7 +581,7 @@ private:
|
|||
|
||||
ExitMethod Scan(u32 begin, u32 end, std::set<u32>& labels);
|
||||
|
||||
BasicBlock DecodeRange(u32 begin, u32 end);
|
||||
NodeBlock DecodeRange(u32 begin, u32 end);
|
||||
|
||||
/**
|
||||
* Decodes a single instruction from Tegra to IR.
|
||||
|
@ -589,33 +589,33 @@ private:
|
|||
* @param pc Program counter. Offset to decode.
|
||||
* @return Next address to decode.
|
||||
*/
|
||||
u32 DecodeInstr(BasicBlock& bb, u32 pc);
|
||||
u32 DecodeInstr(NodeBlock& bb, u32 pc);
|
||||
|
||||
u32 DecodeArithmetic(BasicBlock& bb, u32 pc);
|
||||
u32 DecodeArithmeticImmediate(BasicBlock& bb, u32 pc);
|
||||
u32 DecodeBfe(BasicBlock& bb, u32 pc);
|
||||
u32 DecodeBfi(BasicBlock& bb, u32 pc);
|
||||
u32 DecodeShift(BasicBlock& bb, u32 pc);
|
||||
u32 DecodeArithmeticInteger(BasicBlock& bb, u32 pc);
|
||||
u32 DecodeArithmeticIntegerImmediate(BasicBlock& bb, u32 pc);
|
||||
u32 DecodeArithmeticHalf(BasicBlock& bb, u32 pc);
|
||||
u32 DecodeArithmeticHalfImmediate(BasicBlock& bb, u32 pc);
|
||||
u32 DecodeFfma(BasicBlock& bb, u32 pc);
|
||||
u32 DecodeHfma2(BasicBlock& bb, u32 pc);
|
||||
u32 DecodeConversion(BasicBlock& bb, u32 pc);
|
||||
u32 DecodeMemory(BasicBlock& bb, u32 pc);
|
||||
u32 DecodeFloatSetPredicate(BasicBlock& bb, u32 pc);
|
||||
u32 DecodeIntegerSetPredicate(BasicBlock& bb, u32 pc);
|
||||
u32 DecodeHalfSetPredicate(BasicBlock& bb, u32 pc);
|
||||
u32 DecodePredicateSetRegister(BasicBlock& bb, u32 pc);
|
||||
u32 DecodePredicateSetPredicate(BasicBlock& bb, u32 pc);
|
||||
u32 DecodeRegisterSetPredicate(BasicBlock& bb, u32 pc);
|
||||
u32 DecodeFloatSet(BasicBlock& bb, u32 pc);
|
||||
u32 DecodeIntegerSet(BasicBlock& bb, u32 pc);
|
||||
u32 DecodeHalfSet(BasicBlock& bb, u32 pc);
|
||||
u32 DecodeVideo(BasicBlock& bb, u32 pc);
|
||||
u32 DecodeXmad(BasicBlock& bb, u32 pc);
|
||||
u32 DecodeOther(BasicBlock& bb, u32 pc);
|
||||
u32 DecodeArithmetic(NodeBlock& bb, u32 pc);
|
||||
u32 DecodeArithmeticImmediate(NodeBlock& bb, u32 pc);
|
||||
u32 DecodeBfe(NodeBlock& bb, u32 pc);
|
||||
u32 DecodeBfi(NodeBlock& bb, u32 pc);
|
||||
u32 DecodeShift(NodeBlock& bb, u32 pc);
|
||||
u32 DecodeArithmeticInteger(NodeBlock& bb, u32 pc);
|
||||
u32 DecodeArithmeticIntegerImmediate(NodeBlock& bb, u32 pc);
|
||||
u32 DecodeArithmeticHalf(NodeBlock& bb, u32 pc);
|
||||
u32 DecodeArithmeticHalfImmediate(NodeBlock& bb, u32 pc);
|
||||
u32 DecodeFfma(NodeBlock& bb, u32 pc);
|
||||
u32 DecodeHfma2(NodeBlock& bb, u32 pc);
|
||||
u32 DecodeConversion(NodeBlock& bb, u32 pc);
|
||||
u32 DecodeMemory(NodeBlock& bb, u32 pc);
|
||||
u32 DecodeFloatSetPredicate(NodeBlock& bb, u32 pc);
|
||||
u32 DecodeIntegerSetPredicate(NodeBlock& bb, u32 pc);
|
||||
u32 DecodeHalfSetPredicate(NodeBlock& bb, u32 pc);
|
||||
u32 DecodePredicateSetRegister(NodeBlock& bb, u32 pc);
|
||||
u32 DecodePredicateSetPredicate(NodeBlock& bb, u32 pc);
|
||||
u32 DecodeRegisterSetPredicate(NodeBlock& bb, u32 pc);
|
||||
u32 DecodeFloatSet(NodeBlock& bb, u32 pc);
|
||||
u32 DecodeIntegerSet(NodeBlock& bb, u32 pc);
|
||||
u32 DecodeHalfSet(NodeBlock& bb, u32 pc);
|
||||
u32 DecodeVideo(NodeBlock& bb, u32 pc);
|
||||
u32 DecodeXmad(NodeBlock& bb, u32 pc);
|
||||
u32 DecodeOther(NodeBlock& bb, u32 pc);
|
||||
|
||||
/// Internalizes node's data and returns a managed pointer to a clone of that node
|
||||
Node StoreNode(NodeData&& node_data);
|
||||
|
@ -664,20 +664,20 @@ private:
|
|||
Node GetTemporal(u32 id);
|
||||
|
||||
/// Sets a register. src value must be a number-evaluated node.
|
||||
void SetRegister(BasicBlock& bb, Tegra::Shader::Register dest, Node src);
|
||||
void SetRegister(NodeBlock& bb, Tegra::Shader::Register dest, Node src);
|
||||
/// Sets a predicate. src value must be a bool-evaluated node
|
||||
void SetPredicate(BasicBlock& bb, u64 dest, Node src);
|
||||
void SetPredicate(NodeBlock& bb, u64 dest, Node src);
|
||||
/// Sets an internal flag. src value must be a bool-evaluated node
|
||||
void SetInternalFlag(BasicBlock& bb, InternalFlag flag, Node value);
|
||||
void SetInternalFlag(NodeBlock& bb, InternalFlag flag, Node value);
|
||||
/// Sets a local memory address. address and value must be a number-evaluated node
|
||||
void SetLocalMemory(BasicBlock& bb, Node address, Node value);
|
||||
void SetLocalMemory(NodeBlock& bb, Node address, Node value);
|
||||
/// Sets a temporal. Internally it uses a post-RZ register
|
||||
void SetTemporal(BasicBlock& bb, u32 id, Node value);
|
||||
void SetTemporal(NodeBlock& bb, u32 id, Node value);
|
||||
|
||||
/// Sets internal flags from a float
|
||||
void SetInternalFlagsFromFloat(BasicBlock& bb, Node value, bool sets_cc = true);
|
||||
void SetInternalFlagsFromFloat(NodeBlock& bb, Node value, bool sets_cc = true);
|
||||
/// Sets internal flags from an integer
|
||||
void SetInternalFlagsFromInteger(BasicBlock& bb, Node value, bool sets_cc = true);
|
||||
void SetInternalFlagsFromInteger(NodeBlock& bb, Node value, bool sets_cc = true);
|
||||
|
||||
/// Conditionally absolute/negated float. Absolute is applied first
|
||||
Node GetOperandAbsNegFloat(Node value, bool absolute, bool negate);
|
||||
|
@ -718,12 +718,12 @@ private:
|
|||
/// Extracts a sequence of bits from a node
|
||||
Node BitfieldExtract(Node value, u32 offset, u32 bits);
|
||||
|
||||
void WriteTexInstructionFloat(BasicBlock& bb, Tegra::Shader::Instruction instr,
|
||||
void WriteTexInstructionFloat(NodeBlock& bb, Tegra::Shader::Instruction instr,
|
||||
const Node4& components);
|
||||
|
||||
void WriteTexsInstructionFloat(BasicBlock& bb, Tegra::Shader::Instruction instr,
|
||||
void WriteTexsInstructionFloat(NodeBlock& bb, Tegra::Shader::Instruction instr,
|
||||
const Node4& components);
|
||||
void WriteTexsInstructionHalfFloat(BasicBlock& bb, Tegra::Shader::Instruction instr,
|
||||
void WriteTexsInstructionHalfFloat(NodeBlock& bb, Tegra::Shader::Instruction instr,
|
||||
const Node4& components);
|
||||
|
||||
Node4 GetTexCode(Tegra::Shader::Instruction instr, Tegra::Shader::TextureType texture_type,
|
||||
|
@ -752,16 +752,16 @@ private:
|
|||
Node GetVideoOperand(Node op, bool is_chunk, bool is_signed, Tegra::Shader::VideoType type,
|
||||
u64 byte_height);
|
||||
|
||||
void WriteLogicOperation(BasicBlock& bb, Tegra::Shader::Register dest,
|
||||
void WriteLogicOperation(NodeBlock& bb, Tegra::Shader::Register dest,
|
||||
Tegra::Shader::LogicOperation logic_op, Node op_a, Node op_b,
|
||||
Tegra::Shader::PredicateResultMode predicate_mode,
|
||||
Tegra::Shader::Pred predicate, bool sets_cc);
|
||||
void WriteLop3Instruction(BasicBlock& bb, Tegra::Shader::Register dest, Node op_a, Node op_b,
|
||||
void WriteLop3Instruction(NodeBlock& bb, Tegra::Shader::Register dest, Node op_a, Node op_b,
|
||||
Node op_c, Node imm_lut, bool sets_cc);
|
||||
|
||||
Node TrackCbuf(Node tracked, const BasicBlock& code, s64 cursor);
|
||||
Node TrackCbuf(Node tracked, const NodeBlock& code, s64 cursor);
|
||||
|
||||
std::pair<Node, s64> TrackRegister(const GprNode* tracked, const BasicBlock& code, s64 cursor);
|
||||
std::pair<Node, s64> TrackRegister(const GprNode* tracked, const NodeBlock& code, s64 cursor);
|
||||
|
||||
template <typename... T>
|
||||
Node Operation(OperationCode code, const T*... operands) {
|
||||
|
@ -803,8 +803,8 @@ private:
|
|||
u32 coverage_end{};
|
||||
std::map<std::pair<u32, u32>, ExitMethod> exit_method_map;
|
||||
|
||||
std::map<u32, BasicBlock> basic_blocks;
|
||||
BasicBlock global_code;
|
||||
std::map<u32, NodeBlock> basic_blocks;
|
||||
NodeBlock global_code;
|
||||
|
||||
std::vector<std::unique_ptr<NodeData>> stored_nodes;
|
||||
|
||||
|
|
|
@ -11,7 +11,7 @@
|
|||
namespace VideoCommon::Shader {
|
||||
|
||||
namespace {
|
||||
std::pair<Node, s64> FindOperation(const BasicBlock& code, s64 cursor,
|
||||
std::pair<Node, s64> FindOperation(const NodeBlock& code, s64 cursor,
|
||||
OperationCode operation_code) {
|
||||
for (; cursor >= 0; --cursor) {
|
||||
const Node node = code[cursor];
|
||||
|
@ -24,7 +24,7 @@ std::pair<Node, s64> FindOperation(const BasicBlock& code, s64 cursor,
|
|||
}
|
||||
} // namespace
|
||||
|
||||
Node ShaderIR::TrackCbuf(Node tracked, const BasicBlock& code, s64 cursor) {
|
||||
Node ShaderIR::TrackCbuf(Node tracked, const NodeBlock& code, s64 cursor) {
|
||||
if (const auto cbuf = std::get_if<CbufNode>(tracked)) {
|
||||
// Cbuf found, but it has to be immediate
|
||||
return std::holds_alternative<ImmediateNode>(*cbuf->GetOffset()) ? tracked : nullptr;
|
||||
|
@ -53,7 +53,7 @@ Node ShaderIR::TrackCbuf(Node tracked, const BasicBlock& code, s64 cursor) {
|
|||
return nullptr;
|
||||
}
|
||||
|
||||
std::pair<Node, s64> ShaderIR::TrackRegister(const GprNode* tracked, const BasicBlock& code,
|
||||
std::pair<Node, s64> ShaderIR::TrackRegister(const GprNode* tracked, const NodeBlock& code,
|
||||
s64 cursor) {
|
||||
for (; cursor >= 0; --cursor) {
|
||||
const auto [found_node, new_cursor] = FindOperation(code, cursor, OperationCode::Assign);
|
||||
|
|
Loading…
Reference in a new issue