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gl_shader_decompiler: Reimplement shuffles with platform agnostic intrinsics
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08b2b1080a
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@ -275,6 +275,7 @@ CachedProgram BuildShader(const Device& device, u64 unique_identifier, ProgramTy
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std::string source = fmt::format(R"(// {}
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#version 430 core
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#extension GL_ARB_separate_shader_objects : enable
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#extension GL_ARB_shader_ballot : enable
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#extension GL_ARB_shader_viewport_layer_array : enable
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#extension GL_EXT_shader_image_load_formatted : enable
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#extension GL_NV_gpu_shader5 : enable
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@ -1942,34 +1942,14 @@ private:
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return Vote(operation, "allThreadsEqualNV");
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}
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template <const std::string_view& func>
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Expression Shuffle(Operation operation) {
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const std::string value = VisitOperand(operation, 0).AsFloat();
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if (!device.HasWarpIntrinsics()) {
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LOG_ERROR(Render_OpenGL, "Nvidia shuffle intrinsics are required by this shader");
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// On a "single-thread" device we are either on the same thread or out of bounds. Both
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// cases return the passed value.
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return {value, Type::Float};
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}
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const std::string index = VisitOperand(operation, 1).AsUint();
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const std::string width = VisitOperand(operation, 2).AsUint();
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return {fmt::format("{}({}, {}, {})", func, value, index, width), Type::Float};
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Expression ThreadId(Operation operation) {
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return {"gl_SubGroupInvocationARB", Type::Uint};
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}
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template <const std::string_view& func>
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Expression InRangeShuffle(Operation operation) {
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const std::string index = VisitOperand(operation, 0).AsUint();
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const std::string width = VisitOperand(operation, 1).AsUint();
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if (!device.HasWarpIntrinsics()) {
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// On a "single-thread" device we are only in bounds when the requested index is 0.
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return {fmt::format("({} == 0U)", index), Type::Bool};
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}
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const std::string in_range = code.GenerateTemporary();
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code.AddLine("bool {};", in_range);
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code.AddLine("{}(0U, {}, {}, {});", func, index, width, in_range);
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return {in_range, Type::Bool};
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Expression ShuffleIndexed(Operation operation) {
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const std::string value = VisitOperand(operation, 0).AsFloat();
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const std::string index = VisitOperand(operation, 1).AsUint();
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return {fmt::format("readInvocationARB({}, {})", value, index), Type::Float};
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}
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struct Func final {
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@ -1981,11 +1961,6 @@ private:
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static constexpr std::string_view Or = "Or";
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static constexpr std::string_view Xor = "Xor";
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static constexpr std::string_view Exchange = "Exchange";
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static constexpr std::string_view ShuffleIndexed = "shuffleNV";
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static constexpr std::string_view ShuffleUp = "shuffleUpNV";
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static constexpr std::string_view ShuffleDown = "shuffleDownNV";
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static constexpr std::string_view ShuffleButterfly = "shuffleXorNV";
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};
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static constexpr std::array operation_decompilers = {
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@ -2151,15 +2126,8 @@ private:
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&GLSLDecompiler::VoteAny,
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&GLSLDecompiler::VoteEqual,
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&GLSLDecompiler::Shuffle<Func::ShuffleIndexed>,
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&GLSLDecompiler::Shuffle<Func::ShuffleUp>,
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&GLSLDecompiler::Shuffle<Func::ShuffleDown>,
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&GLSLDecompiler::Shuffle<Func::ShuffleButterfly>,
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&GLSLDecompiler::InRangeShuffle<Func::ShuffleIndexed>,
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&GLSLDecompiler::InRangeShuffle<Func::ShuffleUp>,
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&GLSLDecompiler::InRangeShuffle<Func::ShuffleDown>,
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&GLSLDecompiler::InRangeShuffle<Func::ShuffleButterfly>,
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&GLSLDecompiler::ThreadId,
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&GLSLDecompiler::ShuffleIndexed,
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};
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static_assert(operation_decompilers.size() == static_cast<std::size_t>(OperationCode::Amount));
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@ -1195,46 +1195,16 @@ private:
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return {};
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}
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Id ThreadId(Operation) {
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UNIMPLEMENTED();
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return {};
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}
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Id ShuffleIndexed(Operation) {
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UNIMPLEMENTED();
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return {};
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}
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Id ShuffleUp(Operation) {
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UNIMPLEMENTED();
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return {};
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}
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Id ShuffleDown(Operation) {
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UNIMPLEMENTED();
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return {};
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}
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Id ShuffleButterfly(Operation) {
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UNIMPLEMENTED();
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return {};
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}
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Id InRangeShuffleIndexed(Operation) {
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UNIMPLEMENTED();
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return {};
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}
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Id InRangeShuffleUp(Operation) {
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UNIMPLEMENTED();
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return {};
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}
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Id InRangeShuffleDown(Operation) {
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UNIMPLEMENTED();
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return {};
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}
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Id InRangeShuffleButterfly(Operation) {
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UNIMPLEMENTED();
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return {};
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}
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Id DeclareBuiltIn(spv::BuiltIn builtin, spv::StorageClass storage, Id type,
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const std::string& name) {
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const Id id = OpVariable(type, storage);
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@ -1528,15 +1498,8 @@ private:
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&SPIRVDecompiler::VoteAny,
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&SPIRVDecompiler::VoteEqual,
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&SPIRVDecompiler::ThreadId,
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&SPIRVDecompiler::ShuffleIndexed,
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&SPIRVDecompiler::ShuffleUp,
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&SPIRVDecompiler::ShuffleDown,
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&SPIRVDecompiler::ShuffleButterfly,
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&SPIRVDecompiler::InRangeShuffleIndexed,
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&SPIRVDecompiler::InRangeShuffleUp,
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&SPIRVDecompiler::InRangeShuffleDown,
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&SPIRVDecompiler::InRangeShuffleButterfly,
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};
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static_assert(operation_decompilers.size() == static_cast<std::size_t>(OperationCode::Amount));
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@ -17,6 +17,7 @@ using Tegra::Shader::ShuffleOperation;
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using Tegra::Shader::VoteOperation;
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namespace {
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OperationCode GetOperationCode(VoteOperation vote_op) {
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switch (vote_op) {
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case VoteOperation::All:
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@ -30,6 +31,7 @@ OperationCode GetOperationCode(VoteOperation vote_op) {
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return OperationCode::VoteAll;
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}
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}
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} // Anonymous namespace
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u32 ShaderIR::DecodeWarp(NodeBlock& bb, u32 pc) {
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@ -46,50 +48,50 @@ u32 ShaderIR::DecodeWarp(NodeBlock& bb, u32 pc) {
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break;
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}
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case OpCode::Id::SHFL: {
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Node width = [this, instr] {
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Node mask = instr.shfl.is_mask_imm ? Immediate(static_cast<u32>(instr.shfl.mask_imm))
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: GetRegister(instr.gpr39);
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// Convert the obscure SHFL mask back into GL_NV_shader_thread_shuffle's width. This has
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// been done reversing Nvidia's math. It won't work on all cases due to SHFL having
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// different parameters that don't properly map to GLSL's interface, but it should work
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// for cases emitted by Nvidia's compiler.
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if (instr.shfl.operation == ShuffleOperation::Up) {
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return Operation(
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OperationCode::ILogicalShiftRight,
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Operation(OperationCode::IAdd, std::move(mask), Immediate(-0x2000)),
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Immediate(8));
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} else {
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return Operation(OperationCode::ILogicalShiftRight,
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Operation(OperationCode::IAdd, Immediate(0x201F),
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Operation(OperationCode::INegate, std::move(mask))),
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Immediate(8));
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}
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}();
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const auto [operation, in_range] = [instr]() -> std::pair<OperationCode, OperationCode> {
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switch (instr.shfl.operation) {
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case ShuffleOperation::Idx:
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return {OperationCode::ShuffleIndexed, OperationCode::InRangeShuffleIndexed};
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case ShuffleOperation::Up:
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return {OperationCode::ShuffleUp, OperationCode::InRangeShuffleUp};
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case ShuffleOperation::Down:
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return {OperationCode::ShuffleDown, OperationCode::InRangeShuffleDown};
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case ShuffleOperation::Bfly:
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return {OperationCode::ShuffleButterfly, OperationCode::InRangeShuffleButterfly};
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}
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UNREACHABLE_MSG("Invalid SHFL operation: {}",
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static_cast<u64>(instr.shfl.operation.Value()));
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return {};
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}();
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// Setting the predicate before the register is intentional to avoid overwriting.
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Node mask = instr.shfl.is_mask_imm ? Immediate(static_cast<u32>(instr.shfl.mask_imm))
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: GetRegister(instr.gpr39);
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Node index = instr.shfl.is_index_imm ? Immediate(static_cast<u32>(instr.shfl.index_imm))
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: GetRegister(instr.gpr20);
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SetPredicate(bb, instr.shfl.pred48, Operation(in_range, index, width));
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Node thread_id = Operation(OperationCode::ThreadId);
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Node clamp = Operation(OperationCode::IBitwiseAnd, mask, Immediate(0x1FU));
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Node seg_mask = BitfieldExtract(mask, 8, 16);
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Node neg_seg_mask = Operation(OperationCode::IBitwiseNot, seg_mask);
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Node min_thread_id = Operation(OperationCode::IBitwiseAnd, thread_id, seg_mask);
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Node max_thread_id = Operation(OperationCode::IBitwiseOr, min_thread_id,
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Operation(OperationCode::IBitwiseAnd, clamp, neg_seg_mask));
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Node src_thread_id = [instr, index, neg_seg_mask, min_thread_id, thread_id] {
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switch (instr.shfl.operation) {
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case ShuffleOperation::Idx:
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return Operation(OperationCode::IBitwiseOr,
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Operation(OperationCode::IBitwiseAnd, index, neg_seg_mask),
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min_thread_id);
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case ShuffleOperation::Down:
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return Operation(OperationCode::IAdd, thread_id, index);
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case ShuffleOperation::Up:
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return Operation(OperationCode::IAdd, thread_id,
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Operation(OperationCode::INegate, index));
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case ShuffleOperation::Bfly:
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return Operation(OperationCode::IBitwiseXor, thread_id, index);
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}
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UNREACHABLE();
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return Immediate(0U);
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}();
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Node in_bounds = [instr, src_thread_id, min_thread_id, max_thread_id] {
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if (instr.shfl.operation == ShuffleOperation::Up) {
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return Operation(OperationCode::LogicalIGreaterEqual, src_thread_id, min_thread_id);
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} else {
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return Operation(OperationCode::LogicalILessEqual, src_thread_id, max_thread_id);
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}
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}();
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SetPredicate(bb, instr.shfl.pred48, in_bounds);
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SetRegister(
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bb, instr.gpr0,
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Operation(operation, GetRegister(instr.gpr8), std::move(index), std::move(width)));
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Operation(OperationCode::ShuffleIndexed, GetRegister(instr.gpr8), src_thread_id));
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break;
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}
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default:
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@ -181,15 +181,8 @@ enum class OperationCode {
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VoteAny, /// (bool) -> bool
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VoteEqual, /// (bool) -> bool
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ShuffleIndexed, /// (uint value, uint index, uint width) -> uint
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ShuffleUp, /// (uint value, uint index, uint width) -> uint
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ShuffleDown, /// (uint value, uint index, uint width) -> uint
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ShuffleButterfly, /// (uint value, uint index, uint width) -> uint
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InRangeShuffleIndexed, /// (uint index, uint width) -> bool
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InRangeShuffleUp, /// (uint index, uint width) -> bool
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InRangeShuffleDown, /// (uint index, uint width) -> bool
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InRangeShuffleButterfly, /// (uint index, uint width) -> bool
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ThreadId, /// () -> uint
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ShuffleIndexed, /// (uint value, uint index) -> uint
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Amount,
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};
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