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Merge pull request #2129 from FernandoS27/cntpct
Correct CNTPCT from using CPU Cycles to using Clock Cycles
This commit is contained in:
commit
059465d496
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@ -114,6 +114,8 @@ add_library(common STATIC
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threadsafe_queue.h
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threadsafe_queue.h
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timer.cpp
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timer.cpp
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timer.h
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timer.h
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uint128.cpp
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uint128.h
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vector_math.h
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vector_math.h
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web_result.h
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web_result.h
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)
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)
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41
src/common/uint128.cpp
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41
src/common/uint128.cpp
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@ -0,0 +1,41 @@
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#ifdef _MSC_VER
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#include <intrin.h>
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#pragma intrinsic(_umul128)
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#endif
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#include <cstring>
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#include "common/uint128.h"
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namespace Common {
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u128 Multiply64Into128(u64 a, u64 b) {
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u128 result;
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#ifdef _MSC_VER
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result[0] = _umul128(a, b, &result[1]);
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#else
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unsigned __int128 tmp = a;
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tmp *= b;
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std::memcpy(&result, &tmp, sizeof(u128));
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#endif
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return result;
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}
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std::pair<u64, u64> Divide128On32(u128 dividend, u32 divisor) {
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u64 remainder = dividend[0] % divisor;
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u64 accum = dividend[0] / divisor;
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if (dividend[1] == 0)
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return {accum, remainder};
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// We ignore dividend[1] / divisor as that overflows
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const u64 first_segment = (dividend[1] % divisor) << 32;
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accum += (first_segment / divisor) << 32;
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const u64 second_segment = (first_segment % divisor) << 32;
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accum += (second_segment / divisor);
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remainder += second_segment % divisor;
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if (remainder >= divisor) {
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accum++;
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remainder -= divisor;
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}
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return {accum, remainder};
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}
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} // namespace Common
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14
src/common/uint128.h
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14
src/common/uint128.h
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@ -0,0 +1,14 @@
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#include <utility>
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#include "common/common_types.h"
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namespace Common {
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// This function multiplies 2 u64 values and produces a u128 value;
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u128 Multiply64Into128(u64 a, u64 b);
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// This function divides a u128 by a u32 value and produces two u64 values:
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// the result of division and the remainder
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std::pair<u64, u64> Divide128On32(u128 dividend, u32 divisor);
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} // namespace Common
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@ -12,6 +12,7 @@
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#include "core/core.h"
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#include "core/core.h"
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#include "core/core_cpu.h"
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#include "core/core_cpu.h"
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#include "core/core_timing.h"
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#include "core/core_timing.h"
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#include "core/core_timing_util.h"
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#include "core/gdbstub/gdbstub.h"
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#include "core/gdbstub/gdbstub.h"
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#include "core/hle/kernel/process.h"
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#include "core/hle/kernel/process.h"
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#include "core/hle/kernel/svc.h"
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#include "core/hle/kernel/svc.h"
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@ -119,7 +120,7 @@ public:
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return std::max(parent.core_timing.GetDowncount(), 0);
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return std::max(parent.core_timing.GetDowncount(), 0);
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}
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}
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u64 GetCNTPCT() override {
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u64 GetCNTPCT() override {
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return parent.core_timing.GetTicks();
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return Timing::CpuCyclesToClockCycles(parent.core_timing.GetTicks());
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}
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}
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ARM_Dynarmic& parent;
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ARM_Dynarmic& parent;
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@ -151,7 +152,7 @@ std::unique_ptr<Dynarmic::A64::Jit> ARM_Dynarmic::MakeJit() const {
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config.tpidr_el0 = &cb->tpidr_el0;
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config.tpidr_el0 = &cb->tpidr_el0;
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config.dczid_el0 = 4;
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config.dczid_el0 = 4;
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config.ctr_el0 = 0x8444c004;
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config.ctr_el0 = 0x8444c004;
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config.cntfrq_el0 = 19200000; // Value from fusee.
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config.cntfrq_el0 = Timing::CNTFREQ;
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// Unpredictable instructions
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// Unpredictable instructions
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config.define_unpredictable_behaviour = true;
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config.define_unpredictable_behaviour = true;
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@ -7,6 +7,7 @@
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#include <cinttypes>
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#include <cinttypes>
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#include <limits>
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#include <limits>
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#include "common/logging/log.h"
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#include "common/logging/log.h"
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#include "common/uint128.h"
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namespace Core::Timing {
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namespace Core::Timing {
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@ -60,4 +61,9 @@ s64 nsToCycles(u64 ns) {
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return (BASE_CLOCK_RATE * static_cast<s64>(ns)) / 1000000000;
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return (BASE_CLOCK_RATE * static_cast<s64>(ns)) / 1000000000;
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}
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}
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u64 CpuCyclesToClockCycles(u64 ticks) {
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const u128 temporal = Common::Multiply64Into128(ticks, CNTFREQ);
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return Common::Divide128On32(temporal, static_cast<u32>(BASE_CLOCK_RATE)).first;
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}
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} // namespace Core::Timing
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} // namespace Core::Timing
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@ -11,6 +11,7 @@ namespace Core::Timing {
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// The below clock rate is based on Switch's clockspeed being widely known as 1.020GHz
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// The below clock rate is based on Switch's clockspeed being widely known as 1.020GHz
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// The exact value used is of course unverified.
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// The exact value used is of course unverified.
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constexpr u64 BASE_CLOCK_RATE = 1019215872; // Switch clock speed is 1020MHz un/docked
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constexpr u64 BASE_CLOCK_RATE = 1019215872; // Switch clock speed is 1020MHz un/docked
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constexpr u64 CNTFREQ = 19200000; // Value from fusee.
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inline s64 msToCycles(int ms) {
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inline s64 msToCycles(int ms) {
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// since ms is int there is no way to overflow
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// since ms is int there is no way to overflow
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@ -61,4 +62,6 @@ inline u64 cyclesToMs(s64 cycles) {
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return cycles * 1000 / BASE_CLOCK_RATE;
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return cycles * 1000 / BASE_CLOCK_RATE;
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}
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}
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u64 CpuCyclesToClockCycles(u64 ticks);
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} // namespace Core::Timing
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} // namespace Core::Timing
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