mirror of https://git.h3cjp.net/H3cJP/citra.git
117 lines
4.5 KiB
C++
117 lines
4.5 KiB
C++
// Copyright 2017 Citra Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#pragma once
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#include "video_core/pica/regs_framebuffer.h"
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#include "video_core/pica/regs_lighting.h"
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#include "video_core/pica/regs_pipeline.h"
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#include "video_core/pica/regs_rasterizer.h"
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#include "video_core/pica/regs_shader.h"
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#include "video_core/pica/regs_texturing.h"
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namespace Pica {
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#define PICA_REG_INDEX(field_name) (offsetof(Pica::RegsInternal, field_name) / sizeof(u32))
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struct RegsInternal {
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static constexpr std::size_t NUM_REGS = 0x300;
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union {
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struct {
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INSERT_PADDING_WORDS(0x10);
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u32 trigger_irq;
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INSERT_PADDING_WORDS(0x2f);
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RasterizerRegs rasterizer;
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TexturingRegs texturing;
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FramebufferRegs framebuffer;
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LightingRegs lighting;
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PipelineRegs pipeline;
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ShaderRegs gs;
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ShaderRegs vs;
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INSERT_PADDING_WORDS(0x20);
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};
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std::array<u32, NUM_REGS> reg_array;
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};
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/// Map register indices to names readable by humans
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static const char* GetRegisterName(u16 index);
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};
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static_assert(sizeof(RegsInternal) == RegsInternal::NUM_REGS * sizeof(u32),
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"Regs struct has wrong size");
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#define ASSERT_REG_POSITION(field_name, position) \
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static_assert(offsetof(RegsInternal, field_name) == position * 4, \
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"Field " #field_name " has invalid position")
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ASSERT_REG_POSITION(trigger_irq, 0x10);
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ASSERT_REG_POSITION(rasterizer, 0x40);
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ASSERT_REG_POSITION(rasterizer.cull_mode, 0x40);
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ASSERT_REG_POSITION(rasterizer.viewport_size_x, 0x41);
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ASSERT_REG_POSITION(rasterizer.viewport_size_y, 0x43);
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ASSERT_REG_POSITION(rasterizer.viewport_depth_range, 0x4d);
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ASSERT_REG_POSITION(rasterizer.viewport_depth_near_plane, 0x4e);
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ASSERT_REG_POSITION(rasterizer.vs_output_attributes[0], 0x50);
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ASSERT_REG_POSITION(rasterizer.vs_output_attributes[1], 0x51);
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ASSERT_REG_POSITION(rasterizer.scissor_test, 0x65);
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ASSERT_REG_POSITION(rasterizer.viewport_corner, 0x68);
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ASSERT_REG_POSITION(rasterizer.depthmap_enable, 0x6D);
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ASSERT_REG_POSITION(texturing, 0x80);
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ASSERT_REG_POSITION(texturing.main_config, 0x80);
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ASSERT_REG_POSITION(texturing.texture0, 0x81);
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ASSERT_REG_POSITION(texturing.texture0_format, 0x8e);
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ASSERT_REG_POSITION(texturing.fragment_lighting_enable, 0x8f);
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ASSERT_REG_POSITION(texturing.texture1, 0x91);
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ASSERT_REG_POSITION(texturing.texture1_format, 0x96);
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ASSERT_REG_POSITION(texturing.texture2, 0x99);
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ASSERT_REG_POSITION(texturing.texture2_format, 0x9e);
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ASSERT_REG_POSITION(texturing.proctex, 0xa8);
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ASSERT_REG_POSITION(texturing.proctex_noise_u, 0xa9);
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ASSERT_REG_POSITION(texturing.proctex_noise_v, 0xaa);
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ASSERT_REG_POSITION(texturing.proctex_noise_frequency, 0xab);
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ASSERT_REG_POSITION(texturing.proctex_lut, 0xac);
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ASSERT_REG_POSITION(texturing.proctex_lut_offset, 0xad);
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ASSERT_REG_POSITION(texturing.proctex_lut_config, 0xaf);
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ASSERT_REG_POSITION(texturing.tev_stage0, 0xc0);
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ASSERT_REG_POSITION(texturing.tev_stage1, 0xc8);
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ASSERT_REG_POSITION(texturing.tev_stage2, 0xd0);
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ASSERT_REG_POSITION(texturing.tev_stage3, 0xd8);
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ASSERT_REG_POSITION(texturing.tev_combiner_buffer_input, 0xe0);
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ASSERT_REG_POSITION(texturing.fog_mode, 0xe0);
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ASSERT_REG_POSITION(texturing.fog_color, 0xe1);
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ASSERT_REG_POSITION(texturing.fog_lut_offset, 0xe6);
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ASSERT_REG_POSITION(texturing.fog_lut_data, 0xe8);
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ASSERT_REG_POSITION(texturing.tev_stage4, 0xf0);
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ASSERT_REG_POSITION(texturing.tev_stage5, 0xf8);
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ASSERT_REG_POSITION(texturing.tev_combiner_buffer_color, 0xfd);
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ASSERT_REG_POSITION(framebuffer, 0x100);
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ASSERT_REG_POSITION(framebuffer.output_merger, 0x100);
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ASSERT_REG_POSITION(framebuffer.framebuffer, 0x110);
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ASSERT_REG_POSITION(lighting, 0x140);
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ASSERT_REG_POSITION(pipeline, 0x200);
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ASSERT_REG_POSITION(pipeline.vertex_attributes, 0x200);
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ASSERT_REG_POSITION(pipeline.index_array, 0x227);
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ASSERT_REG_POSITION(pipeline.num_vertices, 0x228);
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ASSERT_REG_POSITION(pipeline.vertex_offset, 0x22a);
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ASSERT_REG_POSITION(pipeline.trigger_draw, 0x22e);
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ASSERT_REG_POSITION(pipeline.trigger_draw_indexed, 0x22f);
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ASSERT_REG_POSITION(pipeline.vs_default_attributes_setup, 0x232);
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ASSERT_REG_POSITION(pipeline.command_buffer, 0x238);
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ASSERT_REG_POSITION(pipeline.gpu_mode, 0x245);
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ASSERT_REG_POSITION(pipeline.triangle_topology, 0x25e);
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ASSERT_REG_POSITION(pipeline.restart_primitive, 0x25f);
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ASSERT_REG_POSITION(gs, 0x280);
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ASSERT_REG_POSITION(vs, 0x2b0);
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#undef ASSERT_REG_POSITION
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} // namespace Pica
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