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https://git.h3cjp.net/H3cJP/citra.git
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Pica: Add debug utilities for dumping shaders.
This commit is contained in:
Tony Wasserka
parent
6ea003c7b5
commit
f37e39deb9
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@ -2,6 +2,7 @@
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// Licensed under GPLv2
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// Refer to the license.txt file included.
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#include <algorithm>
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#include <fstream>
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#include <string>
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@ -55,6 +56,210 @@ void GeometryDumper::Dump() {
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}
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}
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#pragma pack(1)
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struct DVLBHeader {
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enum : u32 {
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MAGIC_WORD = 0x424C5644, // "DVLB"
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};
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u32 magic_word;
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u32 num_programs;
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// u32 dvle_offset_table[];
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};
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static_assert(sizeof(DVLBHeader) == 0x8, "Incorrect structure size");
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struct DVLPHeader {
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enum : u32 {
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MAGIC_WORD = 0x504C5644, // "DVLP"
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};
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u32 magic_word;
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u32 version;
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u32 binary_offset; // relative to DVLP start
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u32 binary_size_words;
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u32 swizzle_patterns_offset;
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u32 swizzle_patterns_num_entries;
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u32 unk2;
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};
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static_assert(sizeof(DVLPHeader) == 0x1C, "Incorrect structure size");
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struct DVLEHeader {
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enum : u32 {
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MAGIC_WORD = 0x454c5644, // "DVLE"
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};
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enum class ShaderType : u8 {
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VERTEX = 0,
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GEOMETRY = 1,
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};
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u32 magic_word;
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u16 pad1;
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ShaderType type;
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u8 pad2;
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u32 main_offset_words; // offset within binary blob
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u32 endmain_offset_words;
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u32 pad3;
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u32 pad4;
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u32 constant_table_offset;
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u32 constant_table_size; // number of entries
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u32 label_table_offset;
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u32 label_table_size;
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u32 output_register_table_offset;
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u32 output_register_table_size;
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u32 uniform_table_offset;
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u32 uniform_table_size;
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u32 symbol_table_offset;
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u32 symbol_table_size;
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};
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static_assert(sizeof(DVLEHeader) == 0x40, "Incorrect structure size");
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#pragma pack()
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void DumpShader(const u32* binary_data, u32 binary_size, const u32* swizzle_data, u32 swizzle_size,
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u32 main_offset, const Regs::VSOutputAttributes* output_attributes)
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{
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// NOTE: Permanently enabling this just trashes hard disks for no reason.
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// Hence, this is currently disabled.
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return;
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struct StuffToWrite {
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u8* pointer;
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u32 size;
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};
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std::vector<StuffToWrite> writing_queue;
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u32 write_offset = 0;
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auto QueueForWriting = [&writing_queue,&write_offset](u8* pointer, u32 size) {
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writing_queue.push_back({pointer, size});
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u32 old_write_offset = write_offset;
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write_offset += size;
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return old_write_offset;
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};
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// First off, try to translate Pica state (one enum for output attribute type and component)
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// into shbin format (separate type and component mask).
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union OutputRegisterInfo {
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enum Type : u64 {
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POSITION = 0,
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COLOR = 2,
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TEXCOORD0 = 3,
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TEXCOORD1 = 5,
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TEXCOORD2 = 6,
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};
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BitField< 0, 64, u64> hex;
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BitField< 0, 16, Type> type;
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BitField<16, 16, u64> id;
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BitField<32, 4, u64> component_mask;
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};
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// This is put into a try-catch block to make sure we notice unknown configurations.
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std::vector<OutputRegisterInfo> output_info_table;
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for (int i = 0; i < 7; ++i) {
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using OutputAttributes = Pica::Regs::VSOutputAttributes;
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// TODO: It's still unclear how the attribute components map to the register!
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// Once we know that, this code probably will not make much sense anymore.
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std::map<OutputAttributes::Semantic, std::pair<OutputRegisterInfo::Type, u32> > map = {
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{ OutputAttributes::POSITION_X, { OutputRegisterInfo::POSITION, 1} },
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{ OutputAttributes::POSITION_Y, { OutputRegisterInfo::POSITION, 2} },
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{ OutputAttributes::POSITION_Z, { OutputRegisterInfo::POSITION, 4} },
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{ OutputAttributes::POSITION_W, { OutputRegisterInfo::POSITION, 8} },
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{ OutputAttributes::COLOR_R, { OutputRegisterInfo::COLOR, 1} },
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{ OutputAttributes::COLOR_G, { OutputRegisterInfo::COLOR, 2} },
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{ OutputAttributes::COLOR_B, { OutputRegisterInfo::COLOR, 4} },
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{ OutputAttributes::COLOR_A, { OutputRegisterInfo::COLOR, 8} },
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{ OutputAttributes::TEXCOORD0_U, { OutputRegisterInfo::TEXCOORD0, 1} },
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{ OutputAttributes::TEXCOORD0_V, { OutputRegisterInfo::TEXCOORD0, 2} },
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{ OutputAttributes::TEXCOORD1_U, { OutputRegisterInfo::TEXCOORD1, 1} },
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{ OutputAttributes::TEXCOORD1_V, { OutputRegisterInfo::TEXCOORD1, 2} },
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{ OutputAttributes::TEXCOORD2_U, { OutputRegisterInfo::TEXCOORD2, 1} },
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{ OutputAttributes::TEXCOORD2_V, { OutputRegisterInfo::TEXCOORD2, 2} }
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};
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for (const auto& semantic : std::vector<OutputAttributes::Semantic>{
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output_attributes[i].map_x,
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output_attributes[i].map_y,
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output_attributes[i].map_z,
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output_attributes[i].map_w }) {
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if (semantic == OutputAttributes::INVALID)
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continue;
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try {
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OutputRegisterInfo::Type type = map.at(semantic).first;
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u32 component_mask = map.at(semantic).second;
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auto it = std::find_if(output_info_table.begin(), output_info_table.end(),
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[&i, &type](const OutputRegisterInfo& info) {
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return info.id == i && info.type == type;
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}
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);
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if (it == output_info_table.end()) {
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output_info_table.push_back({});
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output_info_table.back().type = type;
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output_info_table.back().component_mask = component_mask;
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output_info_table.back().id = i;
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} else {
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it->component_mask = it->component_mask | component_mask;
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}
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} catch (const std::out_of_range& oor) {
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_dbg_assert_msg_(GPU, 0, "Unknown output attribute mapping");
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ERROR_LOG(GPU, "Unknown output attribute mapping: %03x, %03x, %03x, %03x",
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(int)output_attributes[i].map_x.Value(),
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(int)output_attributes[i].map_y.Value(),
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(int)output_attributes[i].map_z.Value(),
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(int)output_attributes[i].map_w.Value());
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}
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}
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}
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struct {
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DVLBHeader header;
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u32 dvle_offset;
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} dvlb{ {DVLBHeader::MAGIC_WORD, 1 } }; // 1 DVLE
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DVLPHeader dvlp{ DVLPHeader::MAGIC_WORD };
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DVLEHeader dvle{ DVLEHeader::MAGIC_WORD };
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QueueForWriting((u8*)&dvlb, sizeof(dvlb));
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u32 dvlp_offset = QueueForWriting((u8*)&dvlp, sizeof(dvlp));
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dvlb.dvle_offset = QueueForWriting((u8*)&dvle, sizeof(dvle));
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// TODO: Reduce the amount of binary code written to relevant portions
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dvlp.binary_offset = write_offset - dvlp_offset;
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dvlp.binary_size_words = binary_size;
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QueueForWriting((u8*)binary_data, binary_size * sizeof(u32));
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dvlp.swizzle_patterns_offset = write_offset - dvlp_offset;
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dvlp.swizzle_patterns_num_entries = swizzle_size;
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u32 dummy = 0;
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for (int i = 0; i < swizzle_size; ++i) {
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QueueForWriting((u8*)&swizzle_data[i], sizeof(swizzle_data[i]));
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QueueForWriting((u8*)&dummy, sizeof(dummy));
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}
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dvle.main_offset_words = main_offset;
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dvle.output_register_table_offset = write_offset - dvlb.dvle_offset;
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dvle.output_register_table_size = output_info_table.size();
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QueueForWriting((u8*)output_info_table.data(), output_info_table.size() * sizeof(OutputRegisterInfo));
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// TODO: Create a label table for "main"
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// Write data to file
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static int dump_index = 0;
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std::string filename = std::string("shader_dump") + std::to_string(++dump_index) + std::string(".shbin");
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std::ofstream file(filename, std::ios_base::out | std::ios_base::binary);
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for (auto& chunk : writing_queue) {
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file.write((char*)chunk.pointer, chunk.size);
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}
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}
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} // namespace
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} // namespace
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@ -35,6 +35,9 @@ private:
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std::vector<Face> faces;
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};
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void DumpShader(const u32* binary_data, u32 binary_size, const u32* swizzle_data, u32 swizzle_size,
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u32 main_offset, const Regs::VSOutputAttributes* output_attributes);
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} // namespace
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} // namespace
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@ -57,7 +57,7 @@ struct Regs {
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INSERT_PADDING_WORDS(0x1);
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union {
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union VSOutputAttributes {
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// Maps components of output vertex attributes to semantics
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enum Semantic : u32
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{
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@ -4,6 +4,7 @@
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#include "pica.h"
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#include "vertex_shader.h"
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#include "debug_utils/debug_utils.h"
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#include <core/mem_map.h>
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#include <common/file_util.h>
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@ -50,6 +51,11 @@ struct VertexShaderState {
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};
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u32 call_stack[8]; // TODO: What is the maximal call stack depth?
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u32* call_stack_pointer;
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struct {
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u32 max_offset; // maximum program counter ever reached
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u32 max_opdesc_id; // maximum swizzle pattern index ever used
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} debug;
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};
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static void ProcessShaderCode(VertexShaderState& state) {
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@ -57,6 +63,7 @@ static void ProcessShaderCode(VertexShaderState& state) {
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bool increment_pc = true;
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bool exit_loop = false;
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const Instruction& instr = *(const Instruction*)state.program_counter;
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state.debug.max_offset = std::max<u32>(state.debug.max_offset, 1 + (state.program_counter - shader_memory));
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const float24* src1_ = (instr.common.src1 < 0x10) ? state.input_register_table[instr.common.src1]
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: (instr.common.src1 < 0x20) ? &state.temporary_registers[instr.common.src1-0x10].x
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@ -88,6 +95,7 @@ static void ProcessShaderCode(VertexShaderState& state) {
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switch (instr.opcode) {
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case Instruction::OpCode::ADD:
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{
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state.debug.max_opdesc_id = std::max<u32>(state.debug.max_opdesc_id, 1+instr.common.operand_desc_id);
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for (int i = 0; i < 4; ++i) {
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if (!swizzle.DestComponentEnabled(i))
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continue;
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@ -100,6 +108,7 @@ static void ProcessShaderCode(VertexShaderState& state) {
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case Instruction::OpCode::MUL:
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{
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state.debug.max_opdesc_id = std::max<u32>(state.debug.max_opdesc_id, 1+instr.common.operand_desc_id);
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for (int i = 0; i < 4; ++i) {
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if (!swizzle.DestComponentEnabled(i))
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continue;
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@ -113,6 +122,7 @@ static void ProcessShaderCode(VertexShaderState& state) {
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case Instruction::OpCode::DP3:
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case Instruction::OpCode::DP4:
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{
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state.debug.max_opdesc_id = std::max<u32>(state.debug.max_opdesc_id, 1+instr.common.operand_desc_id);
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float24 dot = float24::FromFloat32(0.f);
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int num_components = (instr.opcode == Instruction::OpCode::DP3) ? 3 : 4;
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for (int i = 0; i < num_components; ++i)
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@ -130,6 +140,7 @@ static void ProcessShaderCode(VertexShaderState& state) {
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// Reciprocal
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case Instruction::OpCode::RCP:
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{
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state.debug.max_opdesc_id = std::max<u32>(state.debug.max_opdesc_id, 1+instr.common.operand_desc_id);
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for (int i = 0; i < 4; ++i) {
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if (!swizzle.DestComponentEnabled(i))
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continue;
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@ -145,6 +156,7 @@ static void ProcessShaderCode(VertexShaderState& state) {
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// Reciprocal Square Root
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case Instruction::OpCode::RSQ:
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{
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state.debug.max_opdesc_id = std::max<u32>(state.debug.max_opdesc_id, 1+instr.common.operand_desc_id);
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for (int i = 0; i < 4; ++i) {
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if (!swizzle.DestComponentEnabled(i))
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continue;
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@ -159,6 +171,7 @@ static void ProcessShaderCode(VertexShaderState& state) {
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case Instruction::OpCode::MOV:
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{
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state.debug.max_opdesc_id = std::max<u32>(state.debug.max_opdesc_id, 1+instr.common.operand_desc_id);
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for (int i = 0; i < 4; ++i) {
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if (!swizzle.DestComponentEnabled(i))
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continue;
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@ -212,6 +225,8 @@ OutputVertex RunShader(const InputVertex& input, int num_attributes)
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const u32* main = &shader_memory[registers.vs_main_offset];
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state.program_counter = (u32*)main;
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state.debug.max_offset = 0;
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state.debug.max_opdesc_id = 0;
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// Setup input register table
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const auto& attribute_register_map = registers.vs_input_register_map;
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@ -255,6 +270,9 @@ OutputVertex RunShader(const InputVertex& input, int num_attributes)
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state.call_stack_pointer = &state.call_stack[0];
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ProcessShaderCode(state);
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DebugUtils::DumpShader(shader_memory, state.debug.max_offset, swizzle_data,
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state.debug.max_opdesc_id, registers.vs_main_offset,
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registers.vs_output_attributes);
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DEBUG_LOG(GPU, "Output vertex: pos (%.2f, %.2f, %.2f, %.2f), col(%.2f, %.2f, %.2f, %.2f), tc0(%.2f, %.2f)",
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ret.pos.x.ToFloat32(), ret.pos.y.ToFloat32(), ret.pos.z.ToFloat32(), ret.pos.w.ToFloat32(),
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