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https://git.h3cjp.net/H3cJP/citra.git
synced 2024-11-24 09:33:00 +00:00
Merge pull request #5237 from ameerj/nvdec-syncpt
nvdec: Incorporate syncpoint manager
This commit is contained in:
commit
aaf9e39f56
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@ -11,8 +11,9 @@
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namespace Service::Nvidia::Devices {
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nvhost_nvdec::nvhost_nvdec(Core::System& system, std::shared_ptr<nvmap> nvmap_dev)
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: nvhost_nvdec_common(system, std::move(nvmap_dev)) {}
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nvhost_nvdec::nvhost_nvdec(Core::System& system, std::shared_ptr<nvmap> nvmap_dev,
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SyncpointManager& syncpoint_manager)
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: nvhost_nvdec_common(system, std::move(nvmap_dev), syncpoint_manager) {}
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nvhost_nvdec::~nvhost_nvdec() = default;
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NvResult nvhost_nvdec::Ioctl1(Ioctl command, const std::vector<u8>& input,
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@ -11,7 +11,8 @@ namespace Service::Nvidia::Devices {
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class nvhost_nvdec final : public nvhost_nvdec_common {
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public:
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explicit nvhost_nvdec(Core::System& system, std::shared_ptr<nvmap> nvmap_dev);
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explicit nvhost_nvdec(Core::System& system, std::shared_ptr<nvmap> nvmap_dev,
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SyncpointManager& syncpoint_manager);
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~nvhost_nvdec() override;
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NvResult Ioctl1(Ioctl command, const std::vector<u8>& input, std::vector<u8>& output) override;
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@ -11,6 +11,7 @@
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#include "core/core.h"
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#include "core/hle/service/nvdrv/devices/nvhost_nvdec_common.h"
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#include "core/hle/service/nvdrv/devices/nvmap.h"
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#include "core/hle/service/nvdrv/syncpoint_manager.h"
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#include "core/memory.h"
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#include "video_core/memory_manager.h"
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#include "video_core/renderer_base.h"
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@ -36,8 +37,9 @@ std::size_t WriteVectors(std::vector<u8>& dst, const std::vector<T>& src, std::s
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}
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} // Anonymous namespace
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nvhost_nvdec_common::nvhost_nvdec_common(Core::System& system, std::shared_ptr<nvmap> nvmap_dev)
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: nvdevice(system), nvmap_dev(std::move(nvmap_dev)) {}
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nvhost_nvdec_common::nvhost_nvdec_common(Core::System& system, std::shared_ptr<nvmap> nvmap_dev,
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SyncpointManager& syncpoint_manager)
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: nvdevice(system), nvmap_dev(std::move(nvmap_dev)), syncpoint_manager(syncpoint_manager) {}
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nvhost_nvdec_common::~nvhost_nvdec_common() = default;
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NvResult nvhost_nvdec_common::SetNVMAPfd(const std::vector<u8>& input) {
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@ -71,10 +73,15 @@ NvResult nvhost_nvdec_common::Submit(const std::vector<u8>& input, std::vector<u
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offset = SpliceVectors(input, wait_checks, params.syncpoint_count, offset);
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offset = SpliceVectors(input, fences, params.fence_count, offset);
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// TODO(ameerj): For async gpu, utilize fences for syncpoint 'max' increment
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auto& gpu = system.GPU();
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if (gpu.UseNvdec()) {
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for (std::size_t i = 0; i < syncpt_increments.size(); i++) {
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const SyncptIncr& syncpt_incr = syncpt_increments[i];
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fences[i].id = syncpt_incr.id;
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fences[i].value =
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syncpoint_manager.IncreaseSyncpoint(syncpt_incr.id, syncpt_incr.increments);
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}
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}
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for (const auto& cmd_buffer : command_buffers) {
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auto object = nvmap_dev->GetObject(cmd_buffer.memory_id);
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ASSERT_OR_EXECUTE(object, return NvResult::InvalidState;);
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@ -89,7 +96,13 @@ NvResult nvhost_nvdec_common::Submit(const std::vector<u8>& input, std::vector<u
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cmdlist.size() * sizeof(u32));
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gpu.PushCommandBuffer(cmdlist);
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}
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if (gpu.UseNvdec()) {
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fences[0].value = syncpoint_manager.IncreaseSyncpoint(fences[0].id, 1);
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Tegra::ChCommandHeaderList cmdlist{{(4 << 28) | fences[0].id}};
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gpu.PushCommandBuffer(cmdlist);
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}
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std::memcpy(output.data(), ¶ms, sizeof(IoctlSubmit));
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// Some games expect command_buffers to be written back
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offset = sizeof(IoctlSubmit);
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@ -98,6 +111,7 @@ NvResult nvhost_nvdec_common::Submit(const std::vector<u8>& input, std::vector<u
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offset = WriteVectors(output, reloc_shifts, offset);
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offset = WriteVectors(output, syncpt_increments, offset);
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offset = WriteVectors(output, wait_checks, offset);
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offset = WriteVectors(output, fences, offset);
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return NvResult::Success;
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}
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@ -107,9 +121,10 @@ NvResult nvhost_nvdec_common::GetSyncpoint(const std::vector<u8>& input, std::ve
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std::memcpy(¶ms, input.data(), sizeof(IoctlGetSyncpoint));
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LOG_DEBUG(Service_NVDRV, "called GetSyncpoint, id={}", params.param);
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// We found that implementing this causes deadlocks with async gpu, along with degraded
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// performance. TODO: RE the nvdec async implementation
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params.value = 0;
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if (device_syncpoints[params.param] == 0 && system.GPU().UseNvdec()) {
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device_syncpoints[params.param] = syncpoint_manager.AllocateSyncpoint();
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}
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params.value = device_syncpoints[params.param];
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std::memcpy(output.data(), ¶ms, sizeof(IoctlGetSyncpoint));
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return NvResult::Success;
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@ -10,12 +10,16 @@
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#include "common/swap.h"
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#include "core/hle/service/nvdrv/devices/nvdevice.h"
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namespace Service::Nvidia::Devices {
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namespace Service::Nvidia {
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class SyncpointManager;
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namespace Devices {
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class nvmap;
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class nvhost_nvdec_common : public nvdevice {
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public:
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explicit nvhost_nvdec_common(Core::System& system, std::shared_ptr<nvmap> nvmap_dev);
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explicit nvhost_nvdec_common(Core::System& system, std::shared_ptr<nvmap> nvmap_dev,
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SyncpointManager& syncpoint_manager);
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~nvhost_nvdec_common() override;
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protected:
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@ -157,8 +161,10 @@ protected:
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s32_le nvmap_fd{};
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u32_le submit_timeout{};
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std::shared_ptr<nvmap> nvmap_dev;
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SyncpointManager& syncpoint_manager;
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std::array<u32, MaxSyncPoints> device_syncpoints{};
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// This is expected to be ordered, therefore we must use a map, not unordered_map
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std::map<GPUVAddr, BufferMap> buffer_mappings;
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};
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}; // namespace Service::Nvidia::Devices
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}; // namespace Devices
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} // namespace Service::Nvidia
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@ -10,8 +10,9 @@
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#include "video_core/renderer_base.h"
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namespace Service::Nvidia::Devices {
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nvhost_vic::nvhost_vic(Core::System& system, std::shared_ptr<nvmap> nvmap_dev)
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: nvhost_nvdec_common(system, std::move(nvmap_dev)) {}
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nvhost_vic::nvhost_vic(Core::System& system, std::shared_ptr<nvmap> nvmap_dev,
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SyncpointManager& syncpoint_manager)
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: nvhost_nvdec_common(system, std::move(nvmap_dev), syncpoint_manager) {}
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nvhost_vic::~nvhost_vic() = default;
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@ -7,11 +7,11 @@
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#include "core/hle/service/nvdrv/devices/nvhost_nvdec_common.h"
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namespace Service::Nvidia::Devices {
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class nvmap;
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class nvhost_vic final : public nvhost_nvdec_common {
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public:
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explicit nvhost_vic(Core::System& system, std::shared_ptr<nvmap> nvmap_dev);
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explicit nvhost_vic(Core::System& system, std::shared_ptr<nvmap> nvmap_dev,
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SyncpointManager& syncpoint_manager);
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~nvhost_vic();
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NvResult Ioctl1(Ioctl command, const std::vector<u8>& input, std::vector<u8>& output) override;
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@ -55,9 +55,11 @@ Module::Module(Core::System& system) : syncpoint_manager{system.GPU()} {
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devices["/dev/nvdisp_disp0"] = std::make_shared<Devices::nvdisp_disp0>(system, nvmap_dev);
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devices["/dev/nvhost-ctrl"] =
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std::make_shared<Devices::nvhost_ctrl>(system, events_interface, syncpoint_manager);
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devices["/dev/nvhost-nvdec"] = std::make_shared<Devices::nvhost_nvdec>(system, nvmap_dev);
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devices["/dev/nvhost-nvdec"] =
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std::make_shared<Devices::nvhost_nvdec>(system, nvmap_dev, syncpoint_manager);
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devices["/dev/nvhost-nvjpg"] = std::make_shared<Devices::nvhost_nvjpg>(system);
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devices["/dev/nvhost-vic"] = std::make_shared<Devices::nvhost_vic>(system, nvmap_dev);
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devices["/dev/nvhost-vic"] =
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std::make_shared<Devices::nvhost_vic>(system, nvmap_dev, syncpoint_manager);
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}
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Module::~Module() = default;
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@ -33,8 +33,7 @@ CDmaPusher::CDmaPusher(GPU& gpu_)
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: gpu{gpu_}, nvdec_processor(std::make_shared<Nvdec>(gpu)),
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vic_processor(std::make_unique<Vic>(gpu, nvdec_processor)),
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host1x_processor(std::make_unique<Host1x>(gpu)),
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nvdec_sync(std::make_unique<SyncptIncrManager>(gpu)),
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vic_sync(std::make_unique<SyncptIncrManager>(gpu)) {}
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sync_manager(std::make_unique<SyncptIncrManager>(gpu)) {}
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CDmaPusher::~CDmaPusher() = default;
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@ -110,10 +109,10 @@ void CDmaPusher::ExecuteCommand(u32 state_offset, u32 data) {
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const auto syncpoint_id = static_cast<u32>(data & 0xFF);
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const auto cond = static_cast<u32>((data >> 8) & 0xFF);
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if (cond == 0) {
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nvdec_sync->Increment(syncpoint_id);
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sync_manager->Increment(syncpoint_id);
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} else {
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nvdec_sync->IncrementWhenDone(static_cast<u32>(current_class), syncpoint_id);
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nvdec_sync->SignalDone(syncpoint_id);
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sync_manager->SignalDone(
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sync_manager->IncrementWhenDone(static_cast<u32>(current_class), syncpoint_id));
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}
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break;
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}
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const auto syncpoint_id = static_cast<u32>(data & 0xFF);
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const auto cond = static_cast<u32>((data >> 8) & 0xFF);
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if (cond == 0) {
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vic_sync->Increment(syncpoint_id);
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sync_manager->Increment(syncpoint_id);
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} else {
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vic_sync->IncrementWhenDone(static_cast<u32>(current_class), syncpoint_id);
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vic_sync->SignalDone(syncpoint_id);
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sync_manager->SignalDone(
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sync_manager->IncrementWhenDone(static_cast<u32>(current_class), syncpoint_id));
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}
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break;
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}
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@ -116,12 +116,10 @@ private:
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void ThiStateWrite(ThiRegisters& state, u32 state_offset, const std::vector<u32>& arguments);
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GPU& gpu;
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std::shared_ptr<Nvdec> nvdec_processor;
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std::unique_ptr<Vic> vic_processor;
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std::unique_ptr<Host1x> host1x_processor;
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std::unique_ptr<SyncptIncrManager> nvdec_sync;
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std::unique_ptr<SyncptIncrManager> vic_sync;
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std::shared_ptr<Tegra::Nvdec> nvdec_processor;
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std::unique_ptr<Tegra::Vic> vic_processor;
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std::unique_ptr<Tegra::Host1x> host1x_processor;
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std::unique_ptr<SyncptIncrManager> sync_manager;
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ChClassId current_class{};
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ThiRegisters vic_thi_state{};
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ThiRegisters nvdec_thi_state{};
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@ -10,22 +10,14 @@ Tegra::Host1x::Host1x(GPU& gpu_) : gpu(gpu_) {}
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Tegra::Host1x::~Host1x() = default;
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void Tegra::Host1x::StateWrite(u32 offset, u32 arguments) {
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u8* const state_offset = reinterpret_cast<u8*>(&state) + offset * sizeof(u32);
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std::memcpy(state_offset, &arguments, sizeof(u32));
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}
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void Tegra::Host1x::ProcessMethod(Method method, const std::vector<u32>& arguments) {
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StateWrite(static_cast<u32>(method), arguments[0]);
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void Tegra::Host1x::ProcessMethod(Method method, u32 argument) {
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switch (method) {
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case Method::WaitSyncpt:
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Execute(arguments[0]);
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break;
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case Method::LoadSyncptPayload32:
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syncpoint_value = arguments[0];
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syncpoint_value = argument;
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break;
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case Method::WaitSyncpt:
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case Method::WaitSyncpt32:
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Execute(arguments[0]);
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Execute(argument);
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break;
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default:
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UNIMPLEMENTED_MSG("Host1x method 0x{:X}", static_cast<u32>(method));
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@ -34,6 +26,5 @@ void Tegra::Host1x::ProcessMethod(Method method, const std::vector<u32>& argumen
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}
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void Tegra::Host1x::Execute(u32 data) {
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// This method waits on a valid syncpoint.
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// TODO: Implement when proper Async is in place
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gpu.WaitFence(data, syncpoint_value);
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}
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@ -14,64 +14,23 @@ class Nvdec;
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class Host1x {
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public:
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struct Host1xClassRegisters {
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u32 incr_syncpt{};
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u32 incr_syncpt_ctrl{};
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u32 incr_syncpt_error{};
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INSERT_PADDING_WORDS(5);
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u32 wait_syncpt{};
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u32 wait_syncpt_base{};
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u32 wait_syncpt_incr{};
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u32 load_syncpt_base{};
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u32 incr_syncpt_base{};
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u32 clear{};
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u32 wait{};
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u32 wait_with_interrupt{};
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u32 delay_use{};
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u32 tick_count_high{};
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u32 tick_count_low{};
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u32 tick_ctrl{};
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INSERT_PADDING_WORDS(23);
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u32 ind_ctrl{};
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u32 ind_off2{};
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u32 ind_off{};
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std::array<u32, 31> ind_data{};
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INSERT_PADDING_WORDS(1);
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u32 load_syncpoint_payload32{};
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u32 stall_ctrl{};
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u32 wait_syncpt32{};
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u32 wait_syncpt_base32{};
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u32 load_syncpt_base32{};
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u32 incr_syncpt_base32{};
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u32 stall_count_high{};
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u32 stall_count_low{};
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u32 xref_ctrl{};
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u32 channel_xref_high{};
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u32 channel_xref_low{};
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};
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static_assert(sizeof(Host1xClassRegisters) == 0x164, "Host1xClassRegisters is an invalid size");
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enum class Method : u32 {
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WaitSyncpt = offsetof(Host1xClassRegisters, wait_syncpt) / 4,
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LoadSyncptPayload32 = offsetof(Host1xClassRegisters, load_syncpoint_payload32) / 4,
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WaitSyncpt32 = offsetof(Host1xClassRegisters, wait_syncpt32) / 4,
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WaitSyncpt = 0x8,
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LoadSyncptPayload32 = 0x4e,
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WaitSyncpt32 = 0x50,
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};
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explicit Host1x(GPU& gpu);
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~Host1x();
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/// Writes the method into the state, Invoke Execute() if encountered
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void ProcessMethod(Method method, const std::vector<u32>& arguments);
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void ProcessMethod(Method method, u32 argument);
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private:
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/// For Host1x, execute is waiting on a syncpoint previously written into the state
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void Execute(u32 data);
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/// Write argument into the provided offset
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void StateWrite(u32 offset, u32 arguments);
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u32 syncpoint_value{};
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Host1xClassRegisters state{};
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GPU& gpu;
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};
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