mirror of
https://git.h3cjp.net/H3cJP/citra.git
synced 2024-12-28 22:26:55 +00:00
dyncom: Minor cleanup
Narrow scopes for the instruction variables. Remove unnecessary parentheses.
This commit is contained in:
Lioncash
parent
326c451758
commit
7a3e371141
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@ -4207,8 +4207,7 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
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CDP_INST:
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{
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cdp_inst *inst_cream = (cdp_inst *)inst_base->component;
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if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
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if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
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// Undefined instruction here
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cpu->NumInstrsToExecute = 0;
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return num_instrs;
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@ -4231,8 +4230,8 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
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}
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CLZ_INST:
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{
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if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
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clz_inst* inst_cream = (clz_inst*)inst_base->component;
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if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
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RD = clz(RM);
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}
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cpu->Reg[15] += GET_INST_SIZE(cpu);
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@ -4316,10 +4315,11 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
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}
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CPY_INST:
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{
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if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
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mov_inst* inst_cream = (mov_inst*)inst_base->component;
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if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
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RD = SHIFTER_OPERAND;
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if ((inst_cream->Rd == 15)) {
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if (inst_cream->Rd == 15) {
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INC_PC(sizeof(mov_inst));
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goto DISPATCH;
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}
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@ -4331,8 +4331,9 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
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}
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EOR_INST:
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{
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if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
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eor_inst* inst_cream = (eor_inst*)inst_base->component;
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if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
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u32 lop = RN;
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if (inst_cream->Rn == 15) {
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lop += 2 * GET_INST_SIZE(cpu);
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@ -4371,8 +4372,8 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
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}
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LDM_INST:
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{
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if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
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ldst_inst* inst_cream = (ldst_inst*)inst_base->component;
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if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
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inst_cream->get_addr(cpu, inst_cream->inst, addr, 1);
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unsigned int inst = inst_cream->inst;
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@ -4441,8 +4442,9 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
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}
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SXTH_INST:
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{
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if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
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sxth_inst* inst_cream = (sxth_inst*)inst_base->component;
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if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
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unsigned int operand2 = ROTATE_RIGHT_32(RM, 8 * inst_cream->rotate);
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if (BIT(operand2, 15)) {
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operand2 |= 0xffff0000;
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@ -4486,9 +4488,10 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
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}
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LDRCOND_INST:
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{
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ldst_inst *inst_cream = (ldst_inst *)inst_base->component;
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if (CondPassed(cpu, inst_base->cond)) {
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ldst_inst *inst_cream = (ldst_inst *)inst_base->component;
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inst_cream->get_addr(cpu, inst_cream->inst, addr, 1);
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unsigned int value = Memory::Read32(addr);
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if (BIT(CP15_REG(CP15_CONTROL), 22) == 1)
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cpu->Reg[BITS(inst_cream->inst, 12, 15)] = value;
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@ -4512,11 +4515,9 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
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}
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UXTH_INST:
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{
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if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
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uxth_inst* inst_cream = (uxth_inst*)inst_base->component;
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if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
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unsigned int operand2 = ROTATE_RIGHT_32(RM, 8 * inst_cream->rotate)
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& 0xffff;
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RD = operand2;
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RD = ROTATE_RIGHT_32(RM, 8 * inst_cream->rotate) & 0xffff;
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}
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cpu->Reg[15] += GET_INST_SIZE(cpu);
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INC_PC(sizeof(uxth_inst));
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@ -4525,10 +4526,10 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
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}
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UXTAH_INST:
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{
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if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
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uxtah_inst* inst_cream = (uxtah_inst*)inst_base->component;
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if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
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unsigned int operand2 = ROTATE_RIGHT_32(RM, 8 * inst_cream->rotate)
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& 0xffff;
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unsigned int operand2 = ROTATE_RIGHT_32(RM, 8 * inst_cream->rotate) & 0xffff;
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RD = RN + operand2;
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if (inst_cream->Rn == 15 || inst_cream->Rm == 15) {
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LOG_ERROR(Core_ARM11, "invalid operands for UXTAH");
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@ -4542,9 +4543,10 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
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}
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LDRB_INST:
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{
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if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
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ldst_inst* inst_cream = (ldst_inst*)inst_base->component;
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if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
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inst_cream->get_addr(cpu, inst_cream->inst, addr, 1);
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cpu->Reg[BITS(inst_cream->inst, 12, 15)] = Memory::Read8(addr);
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if (BITS(inst_cream->inst, 12, 15) == 15) {
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@ -4559,9 +4561,10 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
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}
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LDRBT_INST:
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{
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if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
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ldst_inst* inst_cream = (ldst_inst*)inst_base->component;
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if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
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inst_cream->get_addr(cpu, inst_cream->inst, addr, 1);
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cpu->Reg[BITS(inst_cream->inst, 12, 15)] = Memory::Read8(addr);
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if (BITS(inst_cream->inst, 12, 15) == 15) {
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@ -4576,8 +4579,8 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
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}
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LDRD_INST:
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{
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if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
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ldst_inst* inst_cream = (ldst_inst*)inst_base->component;
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if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
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// Should check if RD is even-numbered, Rd != 14, addr[0:1] == 0, (CP15_reg1_U == 1 || addr[2] == 0)
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inst_cream->get_addr(cpu, inst_cream->inst, addr, 1);
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@ -4594,8 +4597,8 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
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LDREX_INST:
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{
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if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
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generic_arm_inst* inst_cream = (generic_arm_inst*)inst_base->component;
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if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
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unsigned int read_addr = RN;
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add_exclusive_addr(cpu, read_addr);
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@ -4614,8 +4617,8 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
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}
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LDREXB_INST:
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{
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if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
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generic_arm_inst* inst_cream = (generic_arm_inst*)inst_base->component;
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if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
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unsigned int read_addr = RN;
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add_exclusive_addr(cpu, read_addr);
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@ -4634,8 +4637,8 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
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}
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LDREXH_INST:
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{
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if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
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generic_arm_inst* inst_cream = (generic_arm_inst*)inst_base->component;
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if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
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unsigned int read_addr = RN;
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add_exclusive_addr(cpu, read_addr);
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@ -4654,8 +4657,8 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
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}
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LDREXD_INST:
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{
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if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
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generic_arm_inst* inst_cream = (generic_arm_inst*)inst_base->component;
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if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
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unsigned int read_addr = RN;
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add_exclusive_addr(cpu, read_addr);
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@ -4676,8 +4679,8 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
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}
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LDRH_INST:
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{
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if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
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ldst_inst* inst_cream = (ldst_inst*)inst_base->component;
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if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
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inst_cream->get_addr(cpu, inst_cream->inst, addr, 1);
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cpu->Reg[BITS(inst_cream->inst, 12, 15)] = Memory::Read16(addr);
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if (BITS(inst_cream->inst, 12, 15) == 15) {
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@ -4692,8 +4695,8 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
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}
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LDRSB_INST:
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{
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if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
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ldst_inst* inst_cream = (ldst_inst*)inst_base->component;
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if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
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inst_cream->get_addr(cpu, inst_cream->inst, addr, 1);
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unsigned int value = Memory::Read8(addr);
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if (BIT(value, 7)) {
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@ -4712,8 +4715,8 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
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}
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LDRSH_INST:
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{
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if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
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ldst_inst* inst_cream = (ldst_inst*)inst_base->component;
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if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
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inst_cream->get_addr(cpu, inst_cream->inst, addr, 1);
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unsigned int value = Memory::Read16(addr);
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if (BIT(value, 15)) {
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@ -4732,9 +4735,10 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
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}
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LDRT_INST:
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{
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if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
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ldst_inst* inst_cream = (ldst_inst*)inst_base->component;
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if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
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inst_cream->get_addr(cpu, inst_cream->inst, addr, 1);
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unsigned int value = Memory::Read32(addr);
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cpu->Reg[BITS(inst_cream->inst, 12, 15)] = value;
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@ -4755,8 +4759,9 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
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}
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MCR_INST:
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{
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if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
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mcr_inst* inst_cream = (mcr_inst*)inst_base->component;
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if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
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unsigned int inst = inst_cream->inst;
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if (inst_cream->Rd == 15) {
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DEBUG_MSG;
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@ -4855,8 +4860,9 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
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MCRR_INST:
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MLA_INST:
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{
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if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
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mla_inst* inst_cream = (mla_inst*)inst_base->component;
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if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
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uint64_t rm = RM;
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uint64_t rs = RS;
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uint64_t rn = RN;
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@ -4881,8 +4887,9 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
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}
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MOV_INST:
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{
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if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
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mov_inst* inst_cream = (mov_inst*)inst_base->component;
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if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
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RD = SHIFTER_OPERAND;
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if (inst_cream->S && (inst_cream->Rd == 15)) {
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if (CurrentModeHasSPSR) {
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@ -4907,8 +4914,9 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
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}
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MRC_INST:
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{
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if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
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mrc_inst* inst_cream = (mrc_inst*)inst_base->component;
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if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
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unsigned int inst = inst_cream->inst;
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if (inst_cream->Rd == 15) {
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DEBUG_MSG;
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@ -4964,8 +4972,9 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
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MRRC_INST:
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MRS_INST:
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{
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if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
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mrs_inst* inst_cream = (mrs_inst*)inst_base->component;
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if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
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if (inst_cream->R) {
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RD = cpu->Spsr_copy;
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} else {
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@ -5024,8 +5033,9 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
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}
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MUL_INST:
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{
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if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
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mul_inst* inst_cream = (mul_inst*)inst_base->component;
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if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
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uint64_t rm = RM;
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uint64_t rs = RS;
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RD = static_cast<uint32_t>((rm * rs) & 0xffffffff);
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@ -5628,7 +5638,7 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
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SMLA_INST:
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{
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if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
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if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
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smla_inst* inst_cream = (smla_inst*)inst_base->component;
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int32_t operand1, operand2;
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if (inst_cream->x == 0)
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@ -5709,7 +5719,7 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
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SMLAL_INST:
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{
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if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
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if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
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umlal_inst* inst_cream = (umlal_inst*)inst_base->component;
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long long int rm = RM;
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long long int rs = RS;
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@ -5867,7 +5877,7 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
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SMUL_INST:
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{
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if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
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if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
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smul_inst* inst_cream = (smul_inst*)inst_base->component;
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uint32_t operand1, operand2;
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if (inst_cream->x == 0)
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@ -5888,7 +5898,7 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
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}
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SMULL_INST:
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{
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if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
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if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
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umull_inst* inst_cream = (umull_inst*)inst_base->component;
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int64_t rm = RM;
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int64_t rs = RS;
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@ -5997,9 +6007,10 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
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}
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STM_INST:
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{
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if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
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ldst_inst* inst_cream = (ldst_inst*)inst_base->component;
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unsigned int inst = inst_cream->inst;
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if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
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int i;
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unsigned int Rn = BITS(inst, 16, 19);
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unsigned int old_RN = cpu->Reg[Rn];
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@ -6057,8 +6068,9 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
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}
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SXTB_INST:
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{
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if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
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sxtb_inst* inst_cream = (sxtb_inst*)inst_base->component;
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if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
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if (inst_cream->Rm == 15) {
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LOG_ERROR(Core_ARM11, "invalid operand for SXTB");
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CITRA_IGNORE_EXIT(-1);
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@ -6077,9 +6089,10 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
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}
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STR_INST:
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{
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if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
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ldst_inst* inst_cream = (ldst_inst*)inst_base->component;
|
||||
if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
|
||||
inst_cream->get_addr(cpu, inst_cream->inst, addr, 0);
|
||||
|
||||
unsigned int value = cpu->Reg[BITS(inst_cream->inst, 12, 15)];
|
||||
Memory::Write32(addr, value);
|
||||
}
|
||||
|
|
@ -6090,11 +6103,9 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
|
|||
}
|
||||
UXTB_INST:
|
||||
{
|
||||
if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
|
||||
uxtb_inst* inst_cream = (uxtb_inst*)inst_base->component;
|
||||
if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
|
||||
unsigned int operand2 = ROTATE_RIGHT_32(RM, 8 * inst_cream->rotate)
|
||||
& 0xff;
|
||||
RD = operand2;
|
||||
RD = ROTATE_RIGHT_32(RM, 8 * inst_cream->rotate) & 0xff;
|
||||
}
|
||||
cpu->Reg[15] += GET_INST_SIZE(cpu);
|
||||
INC_PC(sizeof(uxtb_inst));
|
||||
|
|
@ -6103,10 +6114,10 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
|
|||
}
|
||||
UXTAB_INST:
|
||||
{
|
||||
if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
|
||||
uxtab_inst* inst_cream = (uxtab_inst*)inst_base->component;
|
||||
if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
|
||||
unsigned int operand2 = ROTATE_RIGHT_32(RM, 8 * inst_cream->rotate)
|
||||
& 0xff;
|
||||
|
||||
unsigned int operand2 = ROTATE_RIGHT_32(RM, 8 * inst_cream->rotate) & 0xff;
|
||||
RD = RN + operand2;
|
||||
}
|
||||
cpu->Reg[15] += GET_INST_SIZE(cpu);
|
||||
|
|
@ -6116,8 +6127,8 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
|
|||
}
|
||||
STRB_INST:
|
||||
{
|
||||
if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
|
||||
ldst_inst* inst_cream = (ldst_inst*)inst_base->component;
|
||||
if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
|
||||
inst_cream->get_addr(cpu, inst_cream->inst, addr, 0);
|
||||
unsigned int value = cpu->Reg[BITS(inst_cream->inst, 12, 15)] & 0xff;
|
||||
Memory::Write8(addr, value);
|
||||
|
|
@ -6129,8 +6140,8 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
|
|||
}
|
||||
STRBT_INST:
|
||||
{
|
||||
if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
|
||||
ldst_inst* inst_cream = (ldst_inst*)inst_base->component;
|
||||
if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
|
||||
inst_cream->get_addr(cpu, inst_cream->inst, addr, 0);
|
||||
unsigned int value = cpu->Reg[BITS(inst_cream->inst, 12, 15)] & 0xff;
|
||||
Memory::Write8(addr, value);
|
||||
|
|
@ -6142,8 +6153,8 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
|
|||
}
|
||||
STRD_INST:
|
||||
{
|
||||
if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
|
||||
ldst_inst* inst_cream = (ldst_inst*)inst_base->component;
|
||||
if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
|
||||
inst_cream->get_addr(cpu, inst_cream->inst, addr, 0);
|
||||
|
||||
unsigned int value = cpu->Reg[BITS(inst_cream->inst, 12, 15)];
|
||||
|
|
@ -6158,9 +6169,8 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
|
|||
}
|
||||
STREX_INST:
|
||||
{
|
||||
if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
|
||||
generic_arm_inst* inst_cream = (generic_arm_inst*)inst_base->component;
|
||||
|
||||
if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
|
||||
unsigned int write_addr = cpu->Reg[inst_cream->Rn];
|
||||
|
||||
if ((exclusive_detect(cpu, write_addr) == 0) && (cpu->exclusive_state == 1)) {
|
||||
|
|
@ -6181,9 +6191,8 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
|
|||
}
|
||||
STREXB_INST:
|
||||
{
|
||||
if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
|
||||
generic_arm_inst* inst_cream = (generic_arm_inst*)inst_base->component;
|
||||
|
||||
if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
|
||||
unsigned int write_addr = cpu->Reg[inst_cream->Rn];
|
||||
|
||||
if ((exclusive_detect(cpu, write_addr) == 0) && (cpu->exclusive_state == 1)) {
|
||||
|
|
@ -6204,9 +6213,8 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
|
|||
}
|
||||
STREXD_INST:
|
||||
{
|
||||
if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
|
||||
generic_arm_inst* inst_cream = (generic_arm_inst*)inst_base->component;
|
||||
|
||||
if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
|
||||
unsigned int write_addr = cpu->Reg[inst_cream->Rn];
|
||||
|
||||
if ((exclusive_detect(cpu, write_addr) == 0) && (cpu->exclusive_state == 1)) {
|
||||
|
|
@ -6229,9 +6237,8 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
|
|||
}
|
||||
STREXH_INST:
|
||||
{
|
||||
if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
|
||||
generic_arm_inst* inst_cream = (generic_arm_inst*)inst_base->component;
|
||||
|
||||
if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
|
||||
unsigned int write_addr = cpu->Reg[inst_cream->Rn];
|
||||
|
||||
if ((exclusive_detect(cpu, write_addr) == 0) && (cpu->exclusive_state == 1)) {
|
||||
|
|
@ -6252,9 +6259,10 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
|
|||
}
|
||||
STRH_INST:
|
||||
{
|
||||
if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
|
||||
ldst_inst* inst_cream = (ldst_inst*)inst_base->component;
|
||||
if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
|
||||
inst_cream->get_addr(cpu, inst_cream->inst, addr, 0);
|
||||
|
||||
unsigned int value = cpu->Reg[BITS(inst_cream->inst, 12, 15)] & 0xffff;
|
||||
Memory::Write16(addr, value);
|
||||
}
|
||||
|
|
@ -6265,9 +6273,10 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
|
|||
}
|
||||
STRT_INST:
|
||||
{
|
||||
if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
|
||||
ldst_inst* inst_cream = (ldst_inst*)inst_base->component;
|
||||
if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
|
||||
inst_cream->get_addr(cpu, inst_cream->inst, addr, 0);
|
||||
|
||||
unsigned int value = cpu->Reg[BITS(inst_cream->inst, 12, 15)];
|
||||
Memory::Write32(addr, value);
|
||||
}
|
||||
|
|
@ -6313,10 +6322,9 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
|
|||
}
|
||||
SWI_INST:
|
||||
{
|
||||
swi_inst *inst_cream = (swi_inst *)inst_base->component;
|
||||
|
||||
if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond))
|
||||
if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
|
||||
HLE::CallSVC(Memory::Read32(cpu->Reg[15]));
|
||||
}
|
||||
|
||||
cpu->Reg[15] += GET_INST_SIZE(cpu);
|
||||
INC_PC(sizeof(swi_inst));
|
||||
|
|
@ -6325,8 +6333,9 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
|
|||
}
|
||||
SWP_INST:
|
||||
{
|
||||
if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
|
||||
swp_inst* inst_cream = (swp_inst*)inst_base->component;
|
||||
if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
|
||||
|
||||
addr = RN;
|
||||
unsigned int value;
|
||||
value = Memory::Read32(addr);
|
||||
|
|
@ -6341,8 +6350,8 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
|
|||
}
|
||||
SWPB_INST:
|
||||
{
|
||||
if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
|
||||
swp_inst* inst_cream = (swp_inst*)inst_base->component;
|
||||
if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
|
||||
addr = RN;
|
||||
unsigned int value = Memory::Read8(addr);
|
||||
Memory::Write8(addr, (RM & 0xFF));
|
||||
|
|
@ -6355,8 +6364,9 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
|
|||
}
|
||||
SXTAB_INST:
|
||||
{
|
||||
if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
|
||||
sxtab_inst* inst_cream = (sxtab_inst*)inst_base->component;
|
||||
if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
|
||||
|
||||
// R15 should be check
|
||||
if(inst_cream->Rn == 15 || inst_cream->Rm == 15 || inst_cream->Rd ==15){
|
||||
CITRA_IGNORE_EXIT(-1);
|
||||
|
|
@ -6408,8 +6418,9 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
|
|||
|
||||
SXTAH_INST:
|
||||
{
|
||||
if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
|
||||
sxtah_inst* inst_cream = (sxtah_inst*)inst_base->component;
|
||||
if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
|
||||
|
||||
// R15 should be check
|
||||
if(inst_cream->Rn == 15 || inst_cream->Rm == 15 || inst_cream->Rd ==15) {
|
||||
CITRA_IGNORE_EXIT(-1);
|
||||
|
|
@ -6741,7 +6752,7 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
|
|||
}
|
||||
UMLAL_INST:
|
||||
{
|
||||
if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
|
||||
if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
|
||||
umlal_inst* inst_cream = (umlal_inst*)inst_base->component;
|
||||
unsigned long long int rm = RM;
|
||||
unsigned long long int rs = RS;
|
||||
|
|
@ -6764,7 +6775,7 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
|
|||
}
|
||||
UMULL_INST:
|
||||
{
|
||||
if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
|
||||
if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
|
||||
umull_inst* inst_cream = (umull_inst*)inst_base->component;
|
||||
unsigned long long int rm = RM;
|
||||
unsigned long long int rs = RS;
|
||||
|
|
|
|||
Loading…
Reference in a new issue