lux/citra
1
0
Fork 0
mirror of https://git.h3cjp.net/H3cJP/citra.git synced 2024-12-28 06:06:55 +00:00
Code Issues Packages Projects Releases Wiki Activity

Merge pull request #8098 from merryhime/ic-ivau

Browse source 
dynarmic: Invalidate CPU cache on all cores
This commit is contained in:
bunnei 2022-03-28 15:45:52 -07:00 committed by GitHub
parent 7382e7a5c8 1383441b15
commit 642913b0d1
No known key found for this signature in database
GPG key ID: 4AEE18F83AFDEB23
2 changed files with 5 additions and 3 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
externals/dynarmic vendored

@ -1 +1 @@
Subproject commit e1a266b9299be81cc0318c7e25b00388c342704f Subproject commit af2d50288fc537201014c4230bb55ab9018a7438

6
src/core/arm/dynarmic/arm_dynarmic_64.cpp
View file

@ -93,17 +93,19 @@ public:
static constexpr u64 ICACHE_LINE_SIZE = 64; static constexpr u64 ICACHE_LINE_SIZE = 64;
const u64 cache_line_start = value & ~(ICACHE_LINE_SIZE - 1); const u64 cache_line_start = value & ~(ICACHE_LINE_SIZE - 1);
parent.InvalidateCacheRange(cache_line_start, ICACHE_LINE_SIZE); parent.system.InvalidateCpuInstructionCacheRange(cache_line_start, ICACHE_LINE_SIZE);
break; break;
} }
case Dynarmic::A64::InstructionCacheOperation::InvalidateAllToPoU: case Dynarmic::A64::InstructionCacheOperation::InvalidateAllToPoU:
parent.ClearInstructionCache(); parent.system.InvalidateCpuInstructionCaches();
break; break;
case Dynarmic::A64::InstructionCacheOperation::InvalidateAllToPoUInnerSharable: case Dynarmic::A64::InstructionCacheOperation::InvalidateAllToPoUInnerSharable:
default: default:
LOG_DEBUG(Core_ARM, "Unprocesseed instruction cache operation: {}", op); LOG_DEBUG(Core_ARM, "Unprocesseed instruction cache operation: {}", op);
break; break;
} }
parent.jit->HaltExecution();
} }
void ExceptionRaised(u64 pc, Dynarmic::A64::Exception exception) override { void ExceptionRaised(u64 pc, Dynarmic::A64::Exception exception) override {