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https://git.h3cjp.net/H3cJP/citra.git
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Shader: Define a common interface for running vertex shader programs.
This commit is contained in:
bunnei
parent
18527b9e21
commit
3f69c2039d
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@ -11,6 +11,7 @@ set(SRCS
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pica.cpp
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primitive_assembly.cpp
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rasterizer.cpp
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shader/shader.cpp
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shader/shader_interpreter.cpp
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utils.cpp
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video_core.cpp
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@ -35,6 +36,7 @@ set(HEADERS
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primitive_assembly.h
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rasterizer.h
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renderer_base.h
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shader/shader.h
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shader/shader_interpreter.h
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utils.h
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video_core.h
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@ -215,6 +215,9 @@ static inline void WritePicaReg(u32 id, u32 value, u32 mask) {
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unsigned int vertex_cache_pos = 0;
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vertex_cache_ids.fill(-1);
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Shader::UnitState shader_unit;
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Shader::Setup(shader_unit);
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for (unsigned int index = 0; index < regs.num_vertices; ++index)
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{
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unsigned int vertex = is_indexed ? (index_u16 ? index_address_16[index] : index_address_8[index]) : index;
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@ -307,7 +310,7 @@ static inline void WritePicaReg(u32 id, u32 value, u32 mask) {
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&geometry_dumper, _1, _2, _3));
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#endif
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// Send to vertex shader
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output = Shader::RunShader(input, attribute_config.GetNumTotalAttributes(), g_state.regs.vs, g_state.vs);
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output = Shader::Run(shader_unit, input, attribute_config.GetNumTotalAttributes());
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if (is_indexed) {
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vertex_cache[vertex_cache_pos] = output;
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@ -1083,6 +1083,7 @@ private:
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// TODO: Perform proper arithmetic on this!
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float value;
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};
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static_assert(sizeof(float24) == sizeof(float), "Shader JIT assumes float24 is implemented as a 32-bit float");
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/// Struct used to describe current Pica state
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struct State {
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@ -1092,7 +1093,10 @@ struct State {
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/// Vertex shader memory
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struct ShaderSetup {
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struct {
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Math::Vec4<float24> f[96];
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// The float uniforms are accessed by the shader JIT using SSE instructions, and are
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// therefore required to be 16-byte aligned.
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Math::Vec4<float24> MEMORY_ALIGNED16(f[96]);
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std::array<bool, 16> b;
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std::array<Math::Vec4<u8>, 4> i;
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} uniforms;
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105
src/video_core/shader/shader.cpp
Normal file
105
src/video_core/shader/shader.cpp
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@ -0,0 +1,105 @@
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// Copyright 2015 Citra Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#include "common/logging/log.h"
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#include "common/profiler.h"
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#include "video_core/debug_utils/debug_utils.h"
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#include "video_core/pica.h"
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#include "shader.h"
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#include "shader_interpreter.h"
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namespace Pica {
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namespace Shader {
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void Setup(UnitState& state) {
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// TODO(bunnei): This will be used by the JIT in a subsequent commit
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}
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static Common::Profiling::TimingCategory shader_category("Vertex Shader");
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OutputVertex Run(UnitState& state, const InputVertex& input, int num_attributes) {
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auto& config = g_state.regs.vs;
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auto& setup = g_state.vs;
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Common::Profiling::ScopeTimer timer(shader_category);
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state.program_counter = config.main_offset;
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state.debug.max_offset = 0;
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state.debug.max_opdesc_id = 0;
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// Setup input register table
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const auto& attribute_register_map = config.input_register_map;
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if (num_attributes > 0) state.input_registers[attribute_register_map.attribute0_register] = input.attr[0];
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if (num_attributes > 1) state.input_registers[attribute_register_map.attribute1_register] = input.attr[1];
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if (num_attributes > 2) state.input_registers[attribute_register_map.attribute2_register] = input.attr[2];
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if (num_attributes > 3) state.input_registers[attribute_register_map.attribute3_register] = input.attr[3];
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if (num_attributes > 4) state.input_registers[attribute_register_map.attribute4_register] = input.attr[4];
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if (num_attributes > 5) state.input_registers[attribute_register_map.attribute5_register] = input.attr[5];
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if (num_attributes > 6) state.input_registers[attribute_register_map.attribute6_register] = input.attr[6];
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if (num_attributes > 7) state.input_registers[attribute_register_map.attribute7_register] = input.attr[7];
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if (num_attributes > 8) state.input_registers[attribute_register_map.attribute8_register] = input.attr[8];
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if (num_attributes > 9) state.input_registers[attribute_register_map.attribute9_register] = input.attr[9];
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if (num_attributes > 10) state.input_registers[attribute_register_map.attribute10_register] = input.attr[10];
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if (num_attributes > 11) state.input_registers[attribute_register_map.attribute11_register] = input.attr[11];
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if (num_attributes > 12) state.input_registers[attribute_register_map.attribute12_register] = input.attr[12];
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if (num_attributes > 13) state.input_registers[attribute_register_map.attribute13_register] = input.attr[13];
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if (num_attributes > 14) state.input_registers[attribute_register_map.attribute14_register] = input.attr[14];
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if (num_attributes > 15) state.input_registers[attribute_register_map.attribute15_register] = input.attr[15];
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state.conditional_code[0] = false;
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state.conditional_code[1] = false;
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RunInterpreter(state);
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#if PICA_DUMP_SHADERS
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DebugUtils::DumpShader(setup.program_code.data(), state.debug.max_offset, setup.swizzle_data.data(),
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state.debug.max_opdesc_id, config.main_offset,
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g_state.regs.vs_output_attributes); // TODO: Don't hardcode VS here
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#endif
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// Setup output data
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OutputVertex ret;
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// TODO(neobrain): Under some circumstances, up to 16 attributes may be output. We need to
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// figure out what those circumstances are and enable the remaining outputs then.
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for (int i = 0; i < 7; ++i) {
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const auto& output_register_map = g_state.regs.vs_output_attributes[i]; // TODO: Don't hardcode VS here
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u32 semantics[4] = {
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output_register_map.map_x, output_register_map.map_y,
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output_register_map.map_z, output_register_map.map_w
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};
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for (int comp = 0; comp < 4; ++comp) {
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float24* out = ((float24*)&ret) + semantics[comp];
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if (semantics[comp] != Regs::VSOutputAttributes::INVALID) {
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*out = state.output_registers[i][comp];
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} else {
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// Zero output so that attributes which aren't output won't have denormals in them,
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// which would slow us down later.
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memset(out, 0, sizeof(*out));
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}
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}
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}
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// The hardware takes the absolute and saturates vertex colors like this, *before* doing interpolation
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for (int i = 0; i < 4; ++i) {
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ret.color[i] = float24::FromFloat32(
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std::fmin(std::fabs(ret.color[i].ToFloat32()), 1.0f));
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}
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LOG_TRACE(Render_Software, "Output vertex: pos (%.2f, %.2f, %.2f, %.2f), col(%.2f, %.2f, %.2f, %.2f), tc0(%.2f, %.2f)",
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ret.pos.x.ToFloat32(), ret.pos.y.ToFloat32(), ret.pos.z.ToFloat32(), ret.pos.w.ToFloat32(),
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ret.color.x.ToFloat32(), ret.color.y.ToFloat32(), ret.color.z.ToFloat32(), ret.color.w.ToFloat32(),
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ret.tc0.u().ToFloat32(), ret.tc0.v().ToFloat32());
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return ret;
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}
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} // namespace Shader
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} // namespace Pica
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163
src/video_core/shader/shader.h
Normal file
163
src/video_core/shader/shader.h
Normal file
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@ -0,0 +1,163 @@
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// Copyright 2015 Citra Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#pragma once
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#include <boost/container/static_vector.hpp>
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#include <nihstro/shader_binary.h>
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#include "common/common_funcs.h"
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#include "common/common_types.h"
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#include "common/vector_math.h"
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#include "video_core/pica.h"
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using nihstro::RegisterType;
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using nihstro::SourceRegister;
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using nihstro::DestRegister;
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namespace Pica {
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namespace Shader {
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struct InputVertex {
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Math::Vec4<float24> attr[16];
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};
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struct OutputVertex {
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OutputVertex() = default;
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// VS output attributes
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Math::Vec4<float24> pos;
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Math::Vec4<float24> dummy; // quaternions (not implemented, yet)
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Math::Vec4<float24> color;
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Math::Vec2<float24> tc0;
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Math::Vec2<float24> tc1;
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float24 pad[6];
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Math::Vec2<float24> tc2;
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// Padding for optimal alignment
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float24 pad2[4];
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// Attributes used to store intermediate results
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// position after perspective divide
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Math::Vec3<float24> screenpos;
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float24 pad3;
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// Linear interpolation
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// factor: 0=this, 1=vtx
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void Lerp(float24 factor, const OutputVertex& vtx) {
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pos = pos * factor + vtx.pos * (float24::FromFloat32(1) - factor);
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// TODO: Should perform perspective correct interpolation here...
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tc0 = tc0 * factor + vtx.tc0 * (float24::FromFloat32(1) - factor);
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tc1 = tc1 * factor + vtx.tc1 * (float24::FromFloat32(1) - factor);
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tc2 = tc2 * factor + vtx.tc2 * (float24::FromFloat32(1) - factor);
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screenpos = screenpos * factor + vtx.screenpos * (float24::FromFloat32(1) - factor);
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color = color * factor + vtx.color * (float24::FromFloat32(1) - factor);
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}
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// Linear interpolation
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// factor: 0=v0, 1=v1
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static OutputVertex Lerp(float24 factor, const OutputVertex& v0, const OutputVertex& v1) {
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OutputVertex ret = v0;
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ret.Lerp(factor, v1);
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return ret;
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}
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};
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static_assert(std::is_pod<OutputVertex>::value, "Structure is not POD");
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static_assert(sizeof(OutputVertex) == 32 * sizeof(float), "OutputVertex has invalid size");
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/**
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* This structure contains the state information that needs to be unique for a shader unit. The 3DS
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* has four shader units that process shaders in parallel. At the present, Citra only implements a
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* single shader unit that processes all shaders serially. Putting the state information in a struct
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* here will make it easier for us to parallelize the shader processing later.
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*/
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struct UnitState {
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// The registers are accessed by the shader JIT using SSE instructions, and are therefore
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// required to be 16-byte aligned.
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Math::Vec4<float24> MEMORY_ALIGNED16(input_registers[16]);
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Math::Vec4<float24> MEMORY_ALIGNED16(output_registers[16]);
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Math::Vec4<float24> MEMORY_ALIGNED16(temporary_registers[16]);
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u32 program_counter;
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bool conditional_code[2];
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// Two Address registers and one loop counter
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// TODO: How many bits do these actually have?
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s32 address_registers[3];
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enum {
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INVALID_ADDRESS = 0xFFFFFFFF
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};
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struct CallStackElement {
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u32 final_address; // Address upon which we jump to return_address
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u32 return_address; // Where to jump when leaving scope
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u8 repeat_counter; // How often to repeat until this call stack element is removed
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u8 loop_increment; // Which value to add to the loop counter after an iteration
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// TODO: Should this be a signed value? Does it even matter?
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u32 loop_address; // The address where we'll return to after each loop iteration
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};
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// TODO: Is there a maximal size for this?
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boost::container::static_vector<CallStackElement, 16> call_stack;
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struct {
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u32 max_offset; // maximum program counter ever reached
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u32 max_opdesc_id; // maximum swizzle pattern index ever used
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} debug;
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static int InputOffset(const SourceRegister& reg) {
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switch (reg.GetRegisterType()) {
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case RegisterType::Input:
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return (int)offsetof(UnitState, input_registers) + reg.GetIndex()*sizeof(Math::Vec4<float24>);
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case RegisterType::Temporary:
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return (int)offsetof(UnitState, temporary_registers) + reg.GetIndex()*sizeof(Math::Vec4<float24>);
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default:
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UNREACHABLE();
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return 0;
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}
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}
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static int OutputOffset(const DestRegister& reg) {
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switch (reg.GetRegisterType()) {
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case RegisterType::Output:
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return (int)offsetof(UnitState, output_registers) + reg.GetIndex()*sizeof(Math::Vec4<float24>);
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case RegisterType::Temporary:
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return (int)offsetof(UnitState, temporary_registers) + reg.GetIndex()*sizeof(Math::Vec4<float24>);
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default:
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UNREACHABLE();
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return 0;
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}
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}
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};
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/**
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* Performs any shader unit setup that only needs to happen once per shader (as opposed to once per
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* vertex, which would happen within the `Run` function).
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* @param state Shader unit state, must be setup per shader and per shader unit
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*/
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void Setup(UnitState& state);
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/**
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* Runs the currently setup shader
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* @param state Shader unit state, must be setup per shader and per shader unit
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* @param input Input vertex into the shader
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* @param num_attributes The number of vertex shader attributes
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* @return The output vertex, after having been processed by the vertex shader
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*/
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OutputVertex Run(UnitState& state, const InputVertex& input, int num_attributes);
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} // namespace Shader
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} // namespace Pica
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@ -2,18 +2,14 @@
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#include <boost/container/static_vector.hpp>
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#include <boost/range/algorithm.hpp>
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#include <common/file_util.h>
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#include <nihstro/shader_bytecode.h>
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#include "common/profiler.h"
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#include "video_core/pica.h"
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#include "video_core/shader/shader_interpreter.h"
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#include "video_core/debug_utils/debug_utils.h"
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#include "shader.h"
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#include "shader_interpreter.h"
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using nihstro::OpCode;
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using nihstro::Instruction;
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@ -25,42 +21,7 @@ namespace Pica {
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namespace Shader {
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struct ShaderState {
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u32 program_counter;
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const float24* input_register_table[16];
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Math::Vec4<float24> output_registers[16];
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Math::Vec4<float24> temporary_registers[16];
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bool conditional_code[2];
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// Two Address registers and one loop counter
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// TODO: How many bits do these actually have?
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s32 address_registers[3];
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enum {
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INVALID_ADDRESS = 0xFFFFFFFF
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};
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struct CallStackElement {
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u32 final_address; // Address upon which we jump to return_address
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u32 return_address; // Where to jump when leaving scope
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u8 repeat_counter; // How often to repeat until this call stack element is removed
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u8 loop_increment; // Which value to add to the loop counter after an iteration
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// TODO: Should this be a signed value? Does it even matter?
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u32 loop_address; // The address where we'll return to after each loop iteration
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};
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// TODO: Is there a maximal size for this?
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boost::container::static_vector<CallStackElement, 16> call_stack;
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struct {
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u32 max_offset; // maximum program counter ever reached
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u32 max_opdesc_id; // maximum swizzle pattern index ever used
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} debug;
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};
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static void ProcessShaderCode(ShaderState& state) {
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void RunInterpreter(UnitState& state) {
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const auto& uniforms = g_state.vs.uniforms;
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const auto& swizzle_data = g_state.vs.swizzle_data;
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const auto& program_code = g_state.vs.program_code;
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@ -90,7 +51,7 @@ static void ProcessShaderCode(ShaderState& state) {
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const Instruction instr = { program_code[state.program_counter] };
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const SwizzlePattern swizzle = { swizzle_data[instr.common.operand_desc_id] };
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static auto call = [](ShaderState& state, u32 offset, u32 num_instructions,
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static auto call = [](UnitState& state, u32 offset, u32 num_instructions,
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u32 return_offset, u8 repeat_count, u8 loop_increment) {
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state.program_counter = offset - 1; // -1 to make sure when incrementing the PC we end up at the correct offset
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ASSERT(state.call_stack.size() < state.call_stack.capacity());
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@ -101,7 +62,7 @@ static void ProcessShaderCode(ShaderState& state) {
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auto LookupSourceRegister = [&](const SourceRegister& source_reg) -> const float24* {
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switch (source_reg.GetRegisterType()) {
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case RegisterType::Input:
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return state.input_register_table[source_reg.GetIndex()];
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return &state.input_registers[source_reg.GetIndex()].x;
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case RegisterType::Temporary:
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return &state.temporary_registers[source_reg.GetIndex()].x;
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@ -413,7 +374,7 @@ static void ProcessShaderCode(ShaderState& state) {
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default:
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{
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static auto evaluate_condition = [](const ShaderState& state, bool refx, bool refy, Instruction::FlowControlType flow_control) {
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static auto evaluate_condition = [](const UnitState& state, bool refx, bool refy, Instruction::FlowControlType flow_control) {
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bool results[2] = { refx == state.conditional_code[0],
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refy == state.conditional_code[1] };
|
||||
|
||||
|
|
@ -542,88 +503,6 @@ static void ProcessShaderCode(ShaderState& state) {
|
|||
}
|
||||
}
|
||||
|
||||
static Common::Profiling::TimingCategory shader_category("Vertex Shader");
|
||||
|
||||
OutputVertex RunShader(const InputVertex& input, int num_attributes, const Regs::ShaderConfig& config, const State::ShaderSetup& setup) {
|
||||
Common::Profiling::ScopeTimer timer(shader_category);
|
||||
|
||||
ShaderState state;
|
||||
|
||||
state.program_counter = config.main_offset;
|
||||
state.debug.max_offset = 0;
|
||||
state.debug.max_opdesc_id = 0;
|
||||
|
||||
// Setup input register table
|
||||
const auto& attribute_register_map = config.input_register_map;
|
||||
float24 dummy_register;
|
||||
boost::fill(state.input_register_table, &dummy_register);
|
||||
|
||||
if (num_attributes > 0) state.input_register_table[attribute_register_map.attribute0_register] = &input.attr[0].x;
|
||||
if (num_attributes > 1) state.input_register_table[attribute_register_map.attribute1_register] = &input.attr[1].x;
|
||||
if (num_attributes > 2) state.input_register_table[attribute_register_map.attribute2_register] = &input.attr[2].x;
|
||||
if (num_attributes > 3) state.input_register_table[attribute_register_map.attribute3_register] = &input.attr[3].x;
|
||||
if (num_attributes > 4) state.input_register_table[attribute_register_map.attribute4_register] = &input.attr[4].x;
|
||||
if (num_attributes > 5) state.input_register_table[attribute_register_map.attribute5_register] = &input.attr[5].x;
|
||||
if (num_attributes > 6) state.input_register_table[attribute_register_map.attribute6_register] = &input.attr[6].x;
|
||||
if (num_attributes > 7) state.input_register_table[attribute_register_map.attribute7_register] = &input.attr[7].x;
|
||||
if (num_attributes > 8) state.input_register_table[attribute_register_map.attribute8_register] = &input.attr[8].x;
|
||||
if (num_attributes > 9) state.input_register_table[attribute_register_map.attribute9_register] = &input.attr[9].x;
|
||||
if (num_attributes > 10) state.input_register_table[attribute_register_map.attribute10_register] = &input.attr[10].x;
|
||||
if (num_attributes > 11) state.input_register_table[attribute_register_map.attribute11_register] = &input.attr[11].x;
|
||||
if (num_attributes > 12) state.input_register_table[attribute_register_map.attribute12_register] = &input.attr[12].x;
|
||||
if (num_attributes > 13) state.input_register_table[attribute_register_map.attribute13_register] = &input.attr[13].x;
|
||||
if (num_attributes > 14) state.input_register_table[attribute_register_map.attribute14_register] = &input.attr[14].x;
|
||||
if (num_attributes > 15) state.input_register_table[attribute_register_map.attribute15_register] = &input.attr[15].x;
|
||||
|
||||
state.conditional_code[0] = false;
|
||||
state.conditional_code[1] = false;
|
||||
|
||||
ProcessShaderCode(state);
|
||||
#if PICA_DUMP_SHADERS
|
||||
DebugUtils::DumpShader(setup.program_code.data(), state.debug.max_offset, setup.swizzle_data.data(),
|
||||
state.debug.max_opdesc_id, config.main_offset,
|
||||
g_state.regs.vs_output_attributes); // TODO: Don't hardcode VS here
|
||||
#endif
|
||||
|
||||
// Setup output data
|
||||
OutputVertex ret;
|
||||
// TODO(neobrain): Under some circumstances, up to 16 attributes may be output. We need to
|
||||
// figure out what those circumstances are and enable the remaining outputs then.
|
||||
for (int i = 0; i < 7; ++i) {
|
||||
const auto& output_register_map = g_state.regs.vs_output_attributes[i]; // TODO: Don't hardcode VS here
|
||||
|
||||
u32 semantics[4] = {
|
||||
output_register_map.map_x, output_register_map.map_y,
|
||||
output_register_map.map_z, output_register_map.map_w
|
||||
};
|
||||
|
||||
for (int comp = 0; comp < 4; ++comp) {
|
||||
float24* out = ((float24*)&ret) + semantics[comp];
|
||||
if (semantics[comp] != Regs::VSOutputAttributes::INVALID) {
|
||||
*out = state.output_registers[i][comp];
|
||||
} else {
|
||||
// Zero output so that attributes which aren't output won't have denormals in them,
|
||||
// which would slow us down later.
|
||||
memset(out, 0, sizeof(*out));
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
// The hardware takes the absolute and saturates vertex colors like this, *before* doing interpolation
|
||||
for (int i = 0; i < 4; ++i) {
|
||||
ret.color[i] = float24::FromFloat32(
|
||||
std::fmin(std::fabs(ret.color[i].ToFloat32()), 1.0f));
|
||||
}
|
||||
|
||||
LOG_TRACE(Render_Software, "Output vertex: pos (%.2f, %.2f, %.2f, %.2f), col(%.2f, %.2f, %.2f, %.2f), tc0(%.2f, %.2f)",
|
||||
ret.pos.x.ToFloat32(), ret.pos.y.ToFloat32(), ret.pos.z.ToFloat32(), ret.pos.w.ToFloat32(),
|
||||
ret.color.x.ToFloat32(), ret.color.y.ToFloat32(), ret.color.z.ToFloat32(), ret.color.w.ToFloat32(),
|
||||
ret.tc0.u().ToFloat32(), ret.tc0.v().ToFloat32());
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
|
||||
} // namespace
|
||||
|
||||
} // namespace
|
||||
|
|
|
|||
|
|
@ -4,68 +4,15 @@
|
|||
|
||||
#pragma once
|
||||
|
||||
#include <type_traits>
|
||||
|
||||
#include "common/vector_math.h"
|
||||
|
||||
#include "video_core/pica.h"
|
||||
|
||||
#include "shader.h"
|
||||
|
||||
namespace Pica {
|
||||
|
||||
namespace Shader {
|
||||
|
||||
struct InputVertex {
|
||||
Math::Vec4<float24> attr[16];
|
||||
};
|
||||
|
||||
struct OutputVertex {
|
||||
OutputVertex() = default;
|
||||
|
||||
// VS output attributes
|
||||
Math::Vec4<float24> pos;
|
||||
Math::Vec4<float24> dummy; // quaternions (not implemented, yet)
|
||||
Math::Vec4<float24> color;
|
||||
Math::Vec2<float24> tc0;
|
||||
Math::Vec2<float24> tc1;
|
||||
float24 pad[6];
|
||||
Math::Vec2<float24> tc2;
|
||||
|
||||
// Padding for optimal alignment
|
||||
float24 pad2[4];
|
||||
|
||||
// Attributes used to store intermediate results
|
||||
|
||||
// position after perspective divide
|
||||
Math::Vec3<float24> screenpos;
|
||||
float24 pad3;
|
||||
|
||||
// Linear interpolation
|
||||
// factor: 0=this, 1=vtx
|
||||
void Lerp(float24 factor, const OutputVertex& vtx) {
|
||||
pos = pos * factor + vtx.pos * (float24::FromFloat32(1) - factor);
|
||||
|
||||
// TODO: Should perform perspective correct interpolation here...
|
||||
tc0 = tc0 * factor + vtx.tc0 * (float24::FromFloat32(1) - factor);
|
||||
tc1 = tc1 * factor + vtx.tc1 * (float24::FromFloat32(1) - factor);
|
||||
tc2 = tc2 * factor + vtx.tc2 * (float24::FromFloat32(1) - factor);
|
||||
|
||||
screenpos = screenpos * factor + vtx.screenpos * (float24::FromFloat32(1) - factor);
|
||||
|
||||
color = color * factor + vtx.color * (float24::FromFloat32(1) - factor);
|
||||
}
|
||||
|
||||
// Linear interpolation
|
||||
// factor: 0=v0, 1=v1
|
||||
static OutputVertex Lerp(float24 factor, const OutputVertex& v0, const OutputVertex& v1) {
|
||||
OutputVertex ret = v0;
|
||||
ret.Lerp(factor, v1);
|
||||
return ret;
|
||||
}
|
||||
};
|
||||
static_assert(std::is_pod<OutputVertex>::value, "Structure is not POD");
|
||||
static_assert(sizeof(OutputVertex) == 32 * sizeof(float), "OutputVertex has invalid size");
|
||||
|
||||
OutputVertex RunShader(const InputVertex& input, int num_attributes, const Regs::ShaderConfig& config, const State::ShaderSetup& setup);
|
||||
void RunInterpreter(UnitState& state);
|
||||
|
||||
} // namespace
|
||||
|
||||
|
|
|
|||
Loading…
Reference in a new issue